Integrated, Quad RF Transceiver with Observation Path Data Sheet ADRV9026 The complete transceiver subsystem includes automatic and F8B EATURES manual attenuation control, dc offset correction, quadrature error 4 differential transmitters correction (QEC), and digital filtering, eliminating the need for 4 differential receivers these functions in the digital baseband. Other auxiliary functions 2 observation receivers with 2 inputs each such as analog-to-digital converters (ADCs), digital-to-analog Center frequency: 75 MHz to 6000 MHz converters (DACs), and general-purpose input/outputs Maximum receiver bandwidth: 200 MHz (GPIOs) that provide an array of digital control options are also Maximum transmitter large signal bandwidth: 200 MHz integrated. Maximum transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz To achieve a high level of RF performance, the transceiver Fully integrated independent fractional-N radio frequency includes five fully integrated phase-locked loops (PLLs). Two synthesizers PLLs provide low noise and low power fractional-N RF Fully integrated clock synthesizer synthesis for the transmitter and receiver signal paths. A third Multichip phase synchronization for all local oscillators and fully integrated PLL supports an independent local oscillator (LO) baseband clocks mode for the observation receiver. The fourth PLL generates Support for TDD and FDD applications the clocks needed for the converters and digital circuits, and a 24.33 Gbps JESD204B/JESD204C digital interface fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the 9BAPPLICATIONS phase of all LOs and baseband clocks between multiple 3G/4G/5G TDD and FDD massive MIMO, macro and small cell ADRV9026 chips. All voltage controlled oscillators (VCOs) and base stations loop filter components are integrated and adjustable through the 10BGENERAL DESCRIPTION digital control interface. The ADRV9026 is a highly integrated, radio frequency (RF) agile The serial data interface consists of four serializer lanes and four transceiver offering four independently controlled transmitters, deserializer lanes. The interface supports both the JESD204B and dedicated observation receiver inputs for monitoring each JESD204C standards, operating at data rates up to 24.33 Gbps. transmitter channel, four independently controlled receivers, The interface also supports interleaved mode for lower integrated synthesizers, and digital signal processing functions bandwidths, thus reducing the number of high speed data providing a complete transceiver solution. The device provides interface lanes to one. Both fixed and floating-point data the performance demanded by cellular infrastructure applications, formats are supported. The floating-point format allows such as small cell base station radios, macro 3G/4G/5G systems, internal automatic gain control (AGC) to be invisible to the and massive multiple in/multiple out (MIMO) base stations. demodulator device. The receiver subsystem consists of four independent, wide The ADRV9026 is powered directly from 1.0 V, 1.3 V, and bandwidth, direct conversion receivers with wide dynamic 1.8 V regulators and is controlled via a standard serial range. The four independent transmitters use a direct conversion peripheral interface (SPI) serial port. Comprehensive power- modulator resulting in low noise operation with low power down modes are included to minimize power consumption in consumption. The device also includes two wide bandwidth, normal use. The ADRV9026 is packaged in a 14 mm 14 mm, time shared, observation path receivers with two inputs each for 289-ball chip scale ball grid array (CSP BGA). monitoring transmitter outputs. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20192021 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. ADRV9026 Data Sheet T12B ABLE OF CONTENTS Features .............................................................................................. 1 2600 MHz Band .......................................................................... 67 Applications ...................................................................................... 1 3800 MHz Band .......................................................................... 82 General Description ......................................................................... 1 4800 MHz Band .......................................................................... 97 Revision History ............................................................................... 2 5700 MHz Band ........................................................................ 112 Functional Block Diagram .............................................................. 3 Theory of Operation .................................................................... 127 Specifications .................................................................................... 4 General ....................................................................................... 127 Transmitters and Receivers......................................................... 4 Transmitter ............................................................................... 127 Synthesizers, Auxiliary Converters, and Clock References .. 11 Receiver ..................................................................................... 127 Digital Specifications ................................................................. 14 Observation Receiver ............................................................... 127 Power Supply Specifications ..................................................... 15 Clock Input ............................................................................... 127 Current Consumption ............................................................... 16 Synthesizers ............................................................................... 128 Digital Interface and Timing Specifications ........................... 17 SPI Interface .............................................................................. 128 Absolute Maximum Ratings ......................................................... 18 GPIO x Pins ............................................................................. 128 Junction Temperature ............................................................... 18 Auxiliary Converters ............................................................... 128 Reflow Profile .............................................................................. 18 JTAG Boundary Scan .............................................................. 129 Thermal Resistance .................................................................... 18 Applications Information ........................................................... 130 ESD Caution................................................................................ 18 Power Supply Sequence ........................................................... 130 Pin Configuration and Function Descriptions .......................... 19 Data Interface ........................................................................... 130 Typical Performance Characteristics ........................................... 24 Outline Dimensions ..................................................................... 131 75 MHz Band .............................................................................. 24 Ordering Guide ........................................................................ 131 800 MHz Band ............................................................................ 37 1800 MHz Band .......................................................................... 52 REVISION HISTORY 1/2021Rev. B to Rev. C 3/2020Rev. 0 to Rev. A Changes to Features Section and General Description Section ....... 1 Changes to Features Section and General Description Section ....... 1 Changes to Table 1 ........................................................................... 4 Change to Observation Receivers Parameter, Table 1 ..................... 8 Changes to Table 8 ......................................................................... 17 Changed Synthesizers, Auxiliary ADCs, Reference Section to Changes to Figure 2 ........................................................................ 19 Synthesizers, Auxiliary Converters, and Clock References Changes to Typical Performance Characteristics Section ........ 24 Section .............................................................................................. 11 Added 75 MHz Band Section and Figure 3 to Figure 75 Change to Spot Phase Noise: Wideband Parameter, Table 2 ...... 12 Renumbered Sequentially ............................................................. 24 Change to System Reference Inputs Parameter, Table 2 .......... 13 Changes to Figure 84 ..................................................................... 38 Changes to Table 3 ......................................................................... 14 Changes to Figure 155 ................................................................... 50 Changes to Current Consumption Section, Table 5, Table 6, Changes to Figure 171 ................................................................... 53 and Table 7 ...................................................................................... 16 Changes to Figure 313 ................................................................... 77 Changes to Table 8 ......................................................................... 17 Changes to Figure 481 ................................................................. 106 Change to Table 13 ........................................................................ 20 Changes to Figure 519 ................................................................. 113 Changes to General Section and Observation Changes to Data Interface Section, Table 17, Table 18, and Receiver Section ............................................................................ 114 Table 19 .......................................................................................... 130 Added Table 14 Renumbered Sequentially ............................. 114 Changes to Ordering Guide ........................................................ 131 Added JTAG Boundary Scan Section, Table 15, and Table 16 ..... 116 Changes to Data Interface Section, Table 17, Table 18, and 8/2020Rev. A to Rev. B Table 19 .......................................................................................... 117 Changes to Figure 1 .......................................................................... 3 Changes to Table 1 ........................................................................... 6 11/2019Revision 0: Initial Version Changes to TDD OperationFour Receiver Channels Enabled Section .............................................................................. 16 Rev. C Page 2 of 131