Integrated, Quad RF Transceiver with Observation Path Data Sheet ADRV9029 functions such as analog-to-digital converters (ADCs), digital- FEATURES to-analog converters (DACs), and general-purpose input/ 4 differential transmitters outputs (GPIOs) that provide an array of digital control options 4 differential receivers are also integrated. 2 observation receivers with 2 inputs each Center frequency: 75 MHz to 6000 MHz To achieve a high level of RF performance, the transceiver Fully integrated DPD adaptation engine for power amplifier includes five fully integrated phase-locked loops (PLLs). Two linearization PLLs provide low noise and low power fractional-N RF Crest factor reduction engine synthesis for the transmitter and receiver signal paths. A third Maximum receiver bandwidth: 200 MHz fully integrated PLL supports an independent local oscillator (LO) Maximum transmitter large signal bandwidth: 200 MHz mode for the observation receiver. The fourth PLL generates Maximum transmitter synthesis bandwidth: 450 MHz the clocks needed for the converters and digital circuits, and a Maximum observation receiver bandwidth: 450 MHz fifth PLL provides the clock for the serial data interface. Fully integrated independent fractional-N radio frequency A multichip synchronization mechanism synchronizes the synthesizers phase of all LOs and baseband clocks between multiple Fully integrated clock synthesizer ADRV9029 chips. All voltage controlled oscillators (VCOs) and Multichip phase synchronization for all local oscillators and loop filter components are integrated and adjustable through the baseband clocks digital control interface. Support for TDD and FDD applications This device contains a fully integrated, low power digital 24.33 Gbps JESD204B/JESD204C digital interface predistortion (DPD) adaptation engine for use in power APPLICATIONS amplifier linearization. DPD enables use of high efficiency power 3G/4G/5G TDD and FDD massive MIMO, macro and small cell amplifiers, reducing the power consumption of base station radios base stations while also reducing the number of SERDES lanes necessary to interface with baseband processors. GENERAL DESCRIPTION The low power crest factor reduction (CFR) engine of the The ADRV9029 is a highly integrated, radio frequency (RF) agile ADRV9029 reduces the peak to average ratio (PAR) of the transceiver offering four independently controlled transmitters, input signal, enabling higher efficiency transmit line ups while dedicated observation receiver inputs for monitoring each reducing the processing load on baseband processors. transmitter channel, four independently controlled receivers, The serial data interface consists of four serializer lanes and four integrated synthesizers, and digital signal processing functions deserializer lanes. The interface supports both the JESD204B and providing a complete transceiver solution. The device provides JESD204C standards, operating at data rates up to 24.33 Gbps. the performance demanded by cellular infrastructure applications, The interface also supports interleaved mode for lower such as small cell base station radios, macro 3G/4G/5G systems, bandwidths, thus reducing the number of high speed data and massive multiple in/multiple out (MIMO) base stations. interface lanes to one. Both fixed and floating-point data The receiver subsystem consists of four independent, wide formats are supported. The floating-point format allows bandwidth, direct conversion receivers with wide dynamic internal automatic gain control (AGC) to be invisible to the range. The four independent transmitters use a direct conversion demodulator device. modulator resulting in low noise operation with low power The ADRV9029 is powered directly from 1.0 V, 1.3 V, and consumption. The device also includes two wide bandwidth, 1.8 V regulators and is controlled via a standard serial time shared, observation path receivers with two inputs each for monitoring transmitter outputs. peripheral interface (SPI) serial port. Comprehensive power- down modes are included to minimize power consumption in The complete transceiver subsystem includes automatic and normal use. The ADRV9029 is packaged in a 14 mm 14 mm, manual attenuation control, dc offset correction, quadrature error 289-ball chip scale ball grid array (CSP BGA). correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. ADRV9029 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 3800 MHz Band .......................................................................... 82 Applications ...................................................................................... 1 4800 MHz Band .......................................................................... 97 General Description ......................................................................... 1 5700 MHz Band ........................................................................ 112 Revision History ............................................................................... 2 Theory of Operation .................................................................... 127 Functional Block Diagram .............................................................. 3 Gener al ....................................................................................... 127 Specifications .................................................................................... 4 Transmitter ............................................................................... 127 Transmitters and Receivers......................................................... 4 Receiver ..................................................................................... 127 Synthesizers, Auxiliary Converters, and Clock References .. 11 Observation Receiver ............................................................... 127 Digital Specifications ................................................................. 14 Clock Input ............................................................................... 127 Power Supply Specifications ..................................................... 15 Synthesizers ............................................................................... 128 Current Consumption ............................................................... 16 SPI Interface .............................................................................. 128 Digital Interface and Timing Specifications ........................... 17 GPIO x Pins ............................................................................. 128 Absolute Maximum Ratings ......................................................... 18 Auxiliary Converters ............................................................... 128 Junction Temperature ............................................................... 18 Digital Predistortion (DPD) ................................................... 128 Reflow Profile .............................................................................. 18 Crest Factor Reduction (CFR) ............................................... 131 Thermal Resistance .................................................................... 18 JTAG Boundary Scan .............................................................. 131 ESD Caution................................................................................ 18 Applications Information ........................................................... 132 Pin Configuration and Function Descriptions .......................... 19 Power Supply Sequence ........................................................... 132 Typical Performance Characteristics ........................................... 24 Data Interface ........................................................................... 132 75 MHz Band .............................................................................. 24 Outline Dimensions ..................................................................... 133 800 MHz Band ............................................................................ 37 Ordering Guide ........................................................................ 133 1800 MHz Band .......................................................................... 52 2600 MHz Band .......................................................................... 67 REVISION HISTORY 12/2020Revision 0: Initial Version Rev. 0 Page 2 of 133