19-5635 Rev 11/10 DS1230Y/AB 256k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the A14 1 28 V CC absence of external power 27 A12 WE 2 A7 3 26 A13 Data is automatically protected during power A6 4 25 A8 loss A5 5 24 A9 Replaces 32k x 8 volatile static RAM, A4 6 23 A11 A3 OE EEPROM or Flash memory 7 22 A2 8 21 A10 Unlimited write cycles A1 CE 9 20 Low-power CMOS 10 19 A0 DQ7 Read and write access times of 70 ns 11 18 DQ0 DQ6 12 17 Lithium energy source is electrically DQ1 DQ5 13 16 DQ2 disconnected to retain freshness until power is DQ4 14 15 GND DQ3 applied for the first time Full 10% V operating range (DS1230Y) CC 28-Pin Encapsulated Package Optional 5% V operating range 740-mil Extended CC (DS1230AB) Optional industrial temperature range of 34 NC 1 NC 2 33 NC NC -40C to +85C, designated IND 32 A14 3 NC 31 A13 JEDEC standard 28-pin DIP package 4 NC 30 5 A12 V CC PowerCap Module (PCM) package 6 29 A11 WE 7 28 A10 OE - Directly surface-mountable module 27 A9 8 CE 26 A8 9 DQ7 - Replaceable snap-on PowerCap provides 25 10 A7 DQ6 24 A6 11 DQ5 lithium backup battery 23 12 A5 DQ4 22 A4 13 - Standardized pinout for all nonvolatile DQ3 GND V BAT 14 21 A3 DQ2 20 A2 SRAM products 15 DQ1 19 A1 16 DQ0 - Detachment feature on PowerCap allows 18 17 A0 GND easy removal using a regular screwdriver 34-Pin PowerCap Module (PCM) (Uses DS9034PC+ or DS9034PCI+ PowerCap) PIN DESCRIPTION A0 - A14 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V - Power (+5V) CC GND - Ground NC - No Connect 1 of 10 DS1230Y/AB DESCRIPTION The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a condition occurs, the CC lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 static RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices in the Low Profile Module package are specifically designed for surface-mount applications. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. READ MODE The DS1230 devices execute a read cycle whenever (Write Enable) is inactive (high) and (Chip WE CE Enable) and (Output Enable) are active (low). The unique address specified by the 15 address inputs OE (A - A ) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the 0 14 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1230 devices execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during WR write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1230AB provides full functional capability for V greater than 4.75 volts and write protects by CC 4.5 volts. The DS1230Y provides full functional capability for V greater than 4.5 volts and write CC protects by 4.25 volts. Data is maintained in the absence of V without any additional support circuitry. CC The nonvolatile static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs CC automatically write protect themselves, all inputs become dont care, and all outputs become high- impedance. As V falls below approximately 3.0 volts, a power switching circuit connects the lithium CC energy source to RAM to retain data. During power-up, when V rises above approximately 3.0 volts CC the power switching circuit connects external V to RAM and disconnects the lithium energy source. CC Normal RAM operation can resume after V exceeds 4.75 volts for the DS1230AB and 4.5 volts for the CC DS1230Y. FRESHNESS SEAL Each DS1230 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level greater than 4.25 volts, the lithium energy source CC is enabled for battery back-up operation. 2 of 10