ANV32AA3P 1Mb Quad SPI nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV32AA3P is a 1Mb Compatible with Serial Peripheral Interface (SPI) Quad SPI SRAM with a non-volatile SONOS storage element included with each memory cell, organized as Supports SPI Modes 0 and 3 128k words of 8 bits each. The devices are accessed by a high speed Quad SPI-compatible bus. There are Interface options with Single SPI, Dual SPI and different SPI options available: SPI, DPI and QPI. Addi- Quad SPI tionally, in single SPI mode the address bytes and/or the data byte(s) can be clocked in using dual or quad Interface options separately controlled for interface. The ANV32AA3P is enabled through the Instruction, Address and Data Chip Enable pin (E), accessed via serial clock (CLK) and 3 operation modes either with single serial data Modes: Standard, Burst and XIP input (SI) and single serial data output (SO) or dual by 2 bidirectional input / outputs (I/O0 and I/O1) or quad 108 MHz clock rate by 4 bidirectional inputs / outputs (I/O0, I/O1, I/O2, I/ O3). Block Write Protection The Quad SRAM interface provides the fast access & Write Disable Instruction for Software Data Pro- cycle times, ease of use and unlimited READ & WRITE tection endurance of a standard SRAM. Dedicated safety fea- tures support high data accuracy. WRITE and Secure WRITE With Secure WRITE operation the ANV32AA3P READ, fast READ and Secure READ accepts address and data only when the correct 2 Byte CRC, generated from the complete 3 address Bytes 16 Byte User Serial Number and 128 Byte data, has been transmitted. Corrupt data cannot overwrite existing memory content and even Configuration and Status Register valid data would not overwrite on a corrupted address. With configuration register bit 4 the success of the Low Power Hibernate (HIB <3A) Mode Secure WRITE operation can be monitored. In case of Unlimited READ / WRITE Endurance corrupt data, bit 4 will be set volatile to high. With Secure READ operation the ANV32AA3P calcu- Automatic Non-volatile STORE on Power Down lates the correct 2 Byte CRC parallel to data transfer. The 2 Byte CRC is transmitted after 128 Bytes of data Non-Volatile STORE under Instruction and HSB have been read out. Control Data transfer automatically to the non-volatile storage Automatic RECALL to SRAM on Power-Up cells when power loss is detected or in any brown out situation (the PowerSTORE operation). On power-up, Unlimited RECALL Cycles data are automatically restored to the SRAM (the Power-Up RECALL operation). The PowerSTORE 100k STORE Cycles operation can be disabled via Configuration Register settings. 100-Year Non-volatile Data Retention Both STORE and RECALL operations are also avail- 2.7V to 3.6V main Power Supply able under instruction control, STORE can also be hardware controlled via HSB pin. 1.65V to 1.95V I/O Power Supply BLOCK WRITE Protection is enabled by programming Commercial and Industrial Temperatures the status register with 1 of 14 options to protect blocks of the memory. 24 Ball BGA Package (6 x 8) A non-volatile register supports the option of a 8 Byte RoHS-Compliant user defined serial number. This register is under cus- tomer control only. Document Control Nr. 030 Rev 1.0 Anvo-Systems Dresden June, 2018 1 ANV32AA3P BLOCK DIAGRAM FLASH Array 1024 x 1024 Store / Recall HSB Control STORE SRAM RECALL Array V CC Power V CCQ Control 1024 x 1024 V CAP User Serial Number E Column I/O Data I/O Register SCK Instruction Decode HOLD (I/O3) Status Register Column Decoder Control Logic Configuration Register SI (I/O0) Instruction Register SO (I/O1) Address Counter / Decoder WP (I/O2) PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description 123 45 Chip Enable E SCK Serial Clock HSB nc nc nc A Serial Input (SPI Mode) SI or I/O0 I/O 0 in dual or quad mode nc SCK VSS VCC nc B Serial Output (SPI Mode) SO or I/O1 WP I/O 1 in dual or quad mode nc E nc nc C (I/O2) Hold (Suspends Serial Input) HOLD or I/O3 SO SI HOLD VCAP nc I/O 3 in quad mode D (I/O1) (I/O0) (I/O3) Write Protect WP or I/O2 nc nc nc VCCQ nc E I/O 2 in quad mode HSB Hardware Store busy VCC Main Power Supply Voltage VCCQ I/O Power Supply Voltage BGA24 Top View VCAP Capacitor Voltage VSS Ground Serial Interface Description Master: The device that generates the serial clock. Input: The SI, I/O0, I/O1, I/O2 and I/O3 pins are used to transfer data into the device. They receive instruc- Slave: Because the Serial Clock pin (SCK) is always tions, addresses, and data. Data are latched on the an input, the device always operates as a slave. rising edge of the Serial Clock. Transmitter/Receiver: The device has bi-directional Serial Clock: The SCK pin is used to synchronize the pins (SI, I/O0, SO, I/O1, HOLD, I/O3, WP, I/O2 and communication between a master and the device. HSB) designated for data transmission and reception. Instructions, addresses, or data, present on the input In SPI and DPI mode HOLD and WP act as inputs only. pin, are latched on the rising edge of the clock, while data on the output pins are changed after the falling Output: The SO, I/O0, I/O1, I/O2 and I/O3 pins are edge of the clock input. used in read cycles to transfer data out of the device after the falling edge of Serial Clock. Document Control Nr. 030 Rev 1.0 Anvo-Systems Dresden June, 2018 2 Row Decoder