ANV32AA1W Anvo-Systems Dresden 1Mb Serial SPI nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV32AA1W is a 1Mb Compatible with Serial Peripheral Interface (SPI) serial SRAM with a non-volatile SONOS storage ele- ment included with each memory cell, organized as Supports SPI Modes 0 and 3 128k words of 8 bits each. The devices are accessed by a high speed SPI-compatible bus. The 66MHz clock rate ANV32AA1W is enabled through the Chip Enable pin Block Write Protection (E) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Write Disable Instruction for Software Data Pro- Serial Clock (SCK). All programming cycles are self- timed, and no separate ERASE cycle is required before tection STORE. Secure WRITE The serial SRAM provides the fast access & cycle times, ease of use and unlimited read & write endur- Secure READ ance of a standard SRAM. Dedicated safety features 16 Byte User Serial Number supporting high data accuracy. With Secure WRITE operation the ANV32AA1W Hibernate Mode for low Standby Current accepts address and data only when the correct 2 Byte Unlimited Read/Write Endurance CRC, generated from the 17 bit address and 128 Byte data, has been transmitted. Corrupt data cannot over- Automatic Non-volatile STORE on Power Down write existing memory content and even valid data would not overwrite on a corrupted address. With sta- Non-Volatile STORE under Instruction Control tus register bit 4 the success of the Secure WRITE operation can be monitored. In case of corrupt data bit Automatic RECALL to SRAM on Power Up 4 will be set volatile to high. Unlimited RECALL Cycles With Secure READ operation the ANV32AA1W calcu- lates the correct 2 Byte CRC parallel to data transfer. 100k STORE Cycles The 2 Byte CRC is transmitted after 128 Bytes of data have been read out. 100-Year Non-volatile Data Retention Data transfers automatically to the non-volatile storage 2.7V to 3.6V Power Supply cells when power loss is detected or in any brown out situation (the PowerStore operation). On power up, Commercial and Industrial Temperatures data is automatically restored to the SRAM (the Power 8-pin DFN Package Up Recall operation). The PowerStore operation can be disabled via Status RoHS-Compliant Register settings. Both STORE and RECALL operations are also avail- able under instruction control. BLOCK WRITE Protection is enabled by programming the status register with one of four options to protect blocks. A 16 Byte non-volatile register supports the option of a 16 Byte user defined serial number. This register is under customer control only. This product conforms to Anvo-Systems Dresden specifi- Document Control Nr. 004 Rev 1.9 cations 1 November, 2017ANV32AA1W BLOCK DIAGRAM FLASH Array 1024 x 1024 V CC Power V CAP Store Control V SS SRAM Recall Array Store / Recall 1024 x 1024 Control Column I/O Data IO Register E Column Decoder HOLD Instruction Decode SO Control Logic Instruction, and User Serial Number SI SCK Address Counter / Decoder PIN CONFIGURATION PIN DESCRIPTIONS E 8 VCC 1 Signal Name Signal Description 7 SO 2 HOLD Chip Enable E 6 SCK VCAP 3 VSS 4 SI 5 SCK Serial Clock Serial Input SI Top View Serial Output SO DFN Hold (Suspends Serial HOLD Input) VCC Power Supply Voltage VCAP Capacitor Voltage VSS Ground Serial Interface Description Master: The device that generates the serial clock. Serial Clock: The SCK pin is used to synchronize the communication between a master and the device. Slave: Because the Serial Clock pin (SCK) is always Instructions, addresses, or data, present on the SI pin, an input, the device always operates as a slave. are latched on the rising edge of the clock input, while data on the SO pin is changed after the falling edge of Transmitter/Receiver: The device has separate pins the clock input. designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Output: The SO pin is used to transfer data serially out of the device. During a read cycle data is Serial Op-Code: After the device is selected with E shifted out on this pin after the falling edge of the Serial going low, the first byte will be received. This byte Clock. contains the op-code that defines the operations to be performed. Serial Input: The SI pin is used to transfer data serially into the device. It receives instructions, addresses, and Invalid Op-Code: If an invalid op-code is received, no data. Data is latched on the rising edge of the Serial data will be shifted into the device, and the serial output Clock. Document Control Nr. 004 Rev 1.9 Anvo-Systems Dresden November, 2017 2 DFN Row Decoder