ANV22A88A Anvo-Systems Dresden 32k x 8 nvSRAM words of 8 bits each. There are 2 separate modes of FEATURES operation: SRAM mode and non-volatile mode. In High-performance 256kb non-volatile SRAM SRAM mode, the memory operates as an ordinary 25ns Access Time static RAM. In non-volatile operation mode, data is 10ns Output Enable Access Time transferred in parallel from SRAM to the SONOS elements (STORE) or from all of them to SRAM I = 10mA typ. at 25 ns Cycle Time CC (RECALL). In non-volatile mode SRAM functions are I = 2mA typ. at 250 ns Cycle Time CC disabled. Read Last Successful Written Address The SRAM can be read and written an unlimited number of times, while independent non-volatile data Unlimited Read/Write Endurance resides in SONOS elements. Data transfers from the Automatic non-volatile STORE on Power Down or SRAM to the SONOS elements take place Brown Out (POWERSTORE) automatically upon power down or brown out situation Non-volatile STORE under Soft Sequence or (POWERSTORE) using charge stored in a small external capacitor. Hardware (HSB) Control Transfers from the SONOS elements to the SRAM Automatic RECALL to SRAM on Power Up or after (RECALL) take place automatically on power up or Brown Out may be initiated under user control by a software Unlimited RECALL Cycles sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the non- 100k STORE Cycles volatile information is transferred into the SRAM cells. 100-Year non-volatile Data Retention STORE cycles also may be initiated under user control 3.0V to 3.6V Power Supply by a software sequence or by a single pin (HSB). Once a STORE cycle is initiated, further input or output Commercial and Industrial Temperatures are disabled until the cycle is completed. BGA48 (6x8) The POWERTSTORE function can also be enabled or RoHS-Compliant disabled by a software sequence. With Read Last Successful Written Address it is DESCRIPTION possible to read out the 2 byte of address for data were The Anvo-Systems Dresden ANV22A88A is a 256kb last WRITE was successful. SRAM with a non-volatile SONOS storage element included with each memory cell, organized as 32k BLOCK DIAGRAM FLASH Array 512 x 512 V CC STORE A6 A7 V CAP A8 A9 SRAM Array A10 512 x 512 RECALL A11 A12 A13 STORE / A14 HSB RECALL Control DQ0 Column I/O DQ1 DQ2 Column Decoder DQ3 DQ4 DQ5 DQ6 DQ7 G A0 A1 A2 A3 A4 A5 E W This product conforms to Anvo-Systems Dresden specifi- Document Control Nr. 0021 Rev 02 cations 1 October, 2019 Input Buffer Row Decoder Software Detect Power Control A0 - A14ANV22A88A PIN CONFIGURATION PIN DESCRIPTIONS Top View 1 234 56 Signal Name Signal Description A NC G A0 A1 A2 NC A0 - A14 Address Inputs DQ0 - DQ7 Data In/Out B NC NC A3 A4 E NC Chip Enable E DQ0 NC A5 A6 NC DQ4 C Output Enable G Write Enable W VSS DQ1 NC A7 DQ5 VCC D V Power Supply Voltage CC E VCC DQ2 V NC DQ6 VSS CAP V Ground SS V Capacitor Voltage CAP F DQ3 NC A14 NC NC DQ7 Hardware Controlled Store/Busy HSB NC HSB A12 A13 W NC G NC A8 A9 A10 A11 NC H Device Operation Power On Reset The ANV22A88A has two separate modes of opera- tion: In order to prevent data corruption and inadvertent - SRAM mode and WRITE operations during Power-up, all input signals - non-volatile mode. will be ignored and Data Outputs DQ0 - DQ7 will be in The memory operates in SRAM mode as a standard high impedance state. Power On Reset is exited when fast static RAM. Data is transferred in non-volatile V reaches a stable V . Logical signals can CC CCmin mode from SRAM to SONOS elements (STORE) or applied. from SONOS elements to SRAM (RECALL). In this non-volatile mode SRAM functions are disabled. Power-down / Brown Out STORE cycles may be initiated under user control via a software sequence or HSB assertion and are also When V drops during normal operation below CC automatically initiated when the power supply voltage V all external operations will be disabled, the SWITCH level of the chip falls below V . RECALL SWITCH device will ignore any input signals and Data Outputs operations are automatically initiated upon power up (DQ) will be in high impedance state. Power-down and may also occur when the V rises above V , CC SWITCH during self timed Store Operation will not corrupt data after a low power condition. RECALL cycles may also in the memory. Write operation of the current Byte will be initiated by a software sequence. be completed independent from the power supply. Prior to any STORE operation the whole data in the non- Power up volatile memory will be erased to allow STORE operation of new and restore of unchanged data. When the power supply is turned on from V , Chip SS Enable (E) has to follow the V voltage in accordance CC Operating and Stand-by Modes with the definition of V . It must not be allowed to float, IH but could be connected via a suitable pull-up resistor to When Chip Enable (E) is Low, the device is enabled. In V . CC Operating Mode it is consuming I . In the other CC(OP) The Chip Enable signal (E) is edge as well as level case, when Chip Enable (E) is High, the device is in sensitive. This ensures that the device becomes Standby Mode with the reduced Supply Current deselected after Power-Down until V reaches CC I . CC(SB) V and a falling edge of E from the V level has CCmin IH been detected thereafter. This will start the first SRAM READ operation. The ANV22A88A performs a READ cycle whenever E Document Control Nr. 021 Rev 02 Anvo-Systems Dresden October 2019 2