ANV31A81W Anvo-Systems Dresden 256Kb Serial SPI nvSRAM The Anvo-Systems Dresden ANV31A81W is a 256Kb FEATURES serial SRAM with a non-volatile SONOS storage ele- Compatible with Serial Peripheral Interface (SPI) ment included with each memory cell, organized as 32k words of 8 bits each. The devices are accessed by Supports SPI Modes 0 and 3 a high speed SPI-compatible bus. The ANV31A81W is enabled through the Chip Enable pin (E) and accessed 66MHz clock rate via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). Block Write Protection All programming cycles are self-timed, and no separate Write Disable Instruction for Software Data Pro- ERASE cycle is required before STORE. tection The serial SRAM provides the fast access & cycle times, ease of use and unlimited read & write endur- Secure WRITE ance of a normal SRAM. Dedicated safety features supporting high data accuracy. Secure READ With Secure WRITE operation the ANV31A81W 2Byte User Serial Number accepts address and data only when the correct 2 Byte CRC, generated from the 15 bit address and 64 Byte Hibernate Mode for low Standby Current data, is transmitted. Corrupt data cannot overwrite existing memory content and even valid data would not Page and Block Rollover options overwrite on a corrupted address. With status register Unlimited Read/Write Endurance bit 4 the success of the Secure WRITE operation can be monitored. In case of corrupt data bit 4 will be set Non-Volatile STORE under Instruction Control volatile to high. With Secure READ operation the ANV31A81W calculates the correct 2 Byte CRC paral- Automatic RECALL to SRAM on Power Up lel to data transfer. The 2 Byte CRC is transmitted after 64 Bytes of data have been transmitted. Unlimited RECALL Cycles Both STORE and RECALL operations are available 100k STORE Cycles under instruction control. 100-Year Non-volatile Data Retention On power up, data is automatically restored to the SRAM (the Power Up Recall operation). 2.7V to 3.6V Power Supply BLOCK WRITE Protection is enabled by programming Commercial and Industrial Temperatures the status register with one of four options to protect blocks. 8-pin 150 mil SOIC and DFN Packages A 2 Byte non-volatile register supports the option of a 2 RoHS-Compliant Byte user defined serial number. This register is under customer control only. Status register bit 5 will control page and block roll over modes. DESCRIPTION This product conforms to Anvo-Systems Dresden specifi- Document Control Nr. 025 Rev. 1.5 cations 1 September, 2018ANV31A81W BLOCK DIAGRAM FLASH Array 512 x 512 VCC Power Store Control V SS SRAM Recall Array Store / Recall 512 x 512 Control Column I/O Data IO Register E Column Decoder HOLD SO Instruction Decode Control Logic SI SCK Address Counter/ Decoder WP PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description E 8 VCC 1 Chip Enable E 7 SO 2 HOLD SCK Serial Clock 6 SCK WP 3 5 Serial Input VSS 4 SI SI Serial Output SO Top View Hold (Suspends Serial HOLD Input) 8-pin SOP 150 mil and DFN WP Write Protect VCC Power Supply Voltage VSS Ground Serial Interface Description Serial Clock: The SCK pin is used to synchronize the communication between a master and the device. Master: The device that generates the serial clock. Instructions, addresses, or data, present on the SI pin, are latched on the rising edge of the clock input, while Slave: Because the Serial Clock pin (SCK) is always data on the SO pin is changed after the falling edge of an input, the device always operates as a slave. the clock input. Transmitter/Receiver: The device has separate pins MSB: The Most Significant Bit (MSB) is the first bit designated for data transmission (SO) and reception transmitted and received. (SI). Serial Op-Code: After the device is selected with E Serial Output: The SO pin is used to transfer data going low, the first byte will be received. This byte serially out of the device. During a read cycle data is contains the op-code that defines the operations to be shifted out on this pin after the falling edge of the Serial performed. Clock. Invalid Op-Code: If an invalid op-code is received, no Serial Input: The SI pin is used to transfer data serially data will be shifted into the device, and the serial output into the device. It receives instructions, addresses, and pin (SO) will remain in a high impedance state until the data. Data is latched on the rising edge of the Serial falling edge of E is detected. This will re-initialize the Clock. Document Control Nr. 025 Rev. 1.5 Anvo-Systems Dresden September, 2018 2 SOP/ DFN Row Decoder