ANV31A61W Anvo-Systems Dresden 64kb Serial SPI nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV31A61W is a 64kb Compatible with Serial Peripheral Interface (SPI) serial SRAM with a non-volatile SONOS storage ele- ment included with each memory cell, organized as 8k Supports SPI Modes 0 and 3 words of 8 bits each. The devices are accessed by a high speed SPI-compatible bus. The ANV31A61W is 66MHz clock rate enabled through the Chip Enable pin (E) and accessed Block Write Protection via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). Secure WRITE All programming cycles are self-timed, and no separate ERASE cycle is required before STORE. Secure READ The serial SRAM provides the fast access & cycle 2-Byte User Serial Number times, ease of use and unlimited read & write endur- ance of a normal SRAM. Dedicated safety features Hibernate Mode for low Standby Current supporting high data accuracy. Page and block rollover options With Secure WRITE operation the ANV31A61W accepts address and data only when the correct 2-Byte Unlimited Read/Write Endurance CRC, generated from the 13 bit address and 32 Byte data, is transmitted. Corrupt data cannot overwrite Non-Volatile STORE under Instruction Control existing memory content and even valid data would not Automatic RECALL to SRAM on Power Up overwrite on a corrupted address. With status register bit 4 the success of the WRITE operation can be moni- Unlimited RECALL Cycles tored. In case of corrupt data bit 4 will be set volatile to high. With Secure READ operation the ANV31A61W 100k STORE Cycles calculates the correct 2-Byte CRC parallel to data transfer. The 2Byte CRC is transmitted after 32 Bytes 100-Year Non-volatile Data Retention of data have been transmitted. 2.7V to 3.6V Power Supply Data transfer to the non-volatile storage cells occurs when the STORE operation has been initated by Commercial and Industrial Temperatures STORE instruction. Data transfer from non-volatile storage elements to SRAM cells has to be initiated by 8-pin 150 mil SOIC and DFN8 Packages RECALL instruction. RoHS-Compliant On power up, data is automatically restored to the SRAM (the Power Up Recall operation). BLOCK WRITE Protection is enabled by programming the status register with one of four options to protect blocks. A 2-Byte non-volatile register supports the option of a 2-Byte user defined serial number. This register is under customer control only. Status register bit 5 will control page and block roll over modes. This product conforms to Anvo-Systems Dresden specifications Document Control Nr. 026 Rev 1.5 1 September, 2018ANV31A61W BLOCK DIAGRAM FLASH Array 256 x 256 V CC Power Store Control V SS SRAM Recall Array Store / Recall 256 x 256 Control Column I/O Data IO Register E Column Decoder HOLD Instruction Decode SO Control Logic Instruction, User Serial Number and Last SI successful written Address Register SCK Address Counter / Decoder WP PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description VCC E 1 8 Chip Enable E 7 SO 2 HOLD SCK Serial Clock 6 WP SCK 3 5 Serial Input SI VSS 4 SI Serial Output SO Top View Hold (Suspends Serial HOLD Input) 8-pin SOP 150 mil or DFN8 WP Write Protect VCC Power Supply Voltage VSS Ground Clock. Serial Interface Description Serial Clock: The SCK pin is used to synchronize the Master: The device that generates the serial clock. communication between a master and the device. Instructions, addresses, or data, present on the SI pin, Slave: Because the Serial Clock pin (SCK) is always are latched on the rising edge of the clock input, while an input, the device always operates as a slave. data on the SO pin is changed after the falling edge of Transmitter/Receiver: The device has separate pins the clock input. designated for data transmission (SO) and reception MSB: The Most Significant Bit (MSB) is the first bit (SI). transmitted and received. Serial Output: The SO pin is used to transfer data Serial Op-Code: After the device is selected with E serially out of the device. During a read cycle data is going low, the first byte will be received. This byte shifted out on this pin after the falling edge of the Serial contains the op-code that defines the operations to be Clock. performed. Serial Input: The SI pin is used to transfer data serially Invalid Op-Code: If an invalid op-code is received, no into the device. It receives instructions, addresses, and data will be shifted into the device, and the serial output data. Data is latched on the rising edge of the Serial Document Control Nr. 026 Rev 1.5 Anvo-Systems Dresden September, 2018 2 SOP/ DFN Row Decoder