ANV31A81A 256Kb Serial SPI nvSRAM FEATURES DESCRIPTION The Anvo-Systems Dresden ANV31A81A is a 256Kb Compatible with Serial Peripheral Interface (SPI) serial SRAM with a non-volatile SONOS storage ele- ment included with each memory cell, organized as Supports SPI Modes 0 and 3 32k words of 8 bits each. The devices are accessed by a high speed SPI-compatible bus. The ANV31A81A is 66MHz clock rate enabled through the Chip Enable pin (E) and accessed Block Write Protection via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). Secure WRITE All programming cycles are self-timed, and no separate ERASE cycle is required before STORE. Secure READ The serial SRAM provides the fast access & cycle 2-Byte User Serial Number times, ease of use and unlimited read & write endur- ance of a normal SRAM. Dedicated safety features Hibernate Mode for low Standby Current supporting high data accuracy. Page and Block Rollover options With Secure WRITE operation the ANV31A81A accepts address and data only when the correct 2 Byte Unlimited Read/Write Endurance CRC, generated from the 15 bit address and 64 Byte data, is transmitted. Corrupt data cannot overwrite Non-Volatile STORE under Instruction Control existing memory content and even valid data would not Automatic RECALL to SRAM on Power Up overwrite on a corrupted address. With status register bit 4 the success of the Secure WRITE operation can Unlimited RECALL Cycles be monitored. In case of corrupt data bit 4 will be set volatile to high. With Secure READ operation the 100k STORE Cycles ANV31A81A calculates the correct 2-Byte CRC parallel to data transfer. The 2-Byte CRC is transmitted after 64 100-Year Non-volatile Data Retention Bytes of data have been transmitted. 3.0V to 3.6V Power Supply Both STORE and RECALL operations are available under instruction control. Commercial and Industrial Temperatures On power up, data is automatically restored to the 8-pin 150 mil SOIC Package SRAM (the Power Up Recall operation). RoHS-Compliant BLOCK WRITE Protection is enabled by programming the status register with one of four options to protect blocks. A 2-Byte non-volatile register supports the option of a 2-Byte user defined serial number. This register is under customer control only. Status register bit 5 will control page and block roll over modes. Document Control Nr. 037 Rev. 1.0 Anvo-Systems Dresden September, 2018 1 ANV31A81A BLOCK DIAGRAM FLASH Array 512 x 512 VCC Power Store Control V SS SRAM Recall Array Store / Recall 512 x 512 Control Column I/O Data IO Register E Column Decoder HOLD SO Instruction Decode Control Logic SI SCK Address Counter/ Decoder WP PIN CONFIGURATION PIN DESCRIPTIONS Signal Name Signal Description E 8 VCC 1 Chip Enable E 7 SO 2 HOLD SCK Serial Clock 6 SCK WP 3 5 Serial Input VSS 4 SI SI Serial Output SO Top View Hold (Suspends Serial HOLD Input) 8-pin SOP 150 mil WP Write Protect VCC Power Supply Voltage VSS Ground Serial Interface Description Master: The device that generates the serial clock. Serial Clock: The SCK pin is used to synchronize the communication between a master and the device. Slave: Because the Serial Clock pin (SCK) is always Instructions, addresses, or data, present on the SI pin, an input, the device always operates as a slave. are latched on the rising edge of the clock input, while data on the SO pin is changed after the falling edge of Transmitter/Receiver: The device has separate pins the clock input. designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Output: The SO pin is used to transfer data serially out of the device. During a read cycle data is Serial Op-Code: After the device is selected with E shifted out on this pin after the falling edge of the Serial going low, the first byte will be received. This byte Clock. contains the op-code that defines the operations to be performed. Serial Input: The SI pin is used to transfer data serially into the device. It receives instructions, addresses, and Invalid Op-Code: If an invalid op-code is received, no data. Data is latched on the rising edge of the Serial data will be shifted into the device, and the serial output Clock. Document Control Nr. 037 Rev. 1.0 Anvo-Systems Dresden September, 2018 2 SOP8 Row Decoder