Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY14V101LA CY14V101NA 1-Mbit (128 K 8/64 K 16) nvSRAM 1-Mbit (128 K 8/64 K 16) nvSRAM Features Functional Description 25 ns and 45 ns access times The Cypress CY14V101LA/CY14V101NA is a fast static RAM, with a non-volatile element in each memory cell. The memory is Internally organized as 128 K 8 (CY14V101LA) or 64 K 16 organized as 128 K bytes of 8 bits each or 64 K words of 16 bits (CY14V101NA) each. The embedded non-volatile elements incorporate Hands off automatic STORE on power down with only a small QuantumTrap technology, producing the worlds most reliable capacitor non-volatile memory. The SRAM provides infinite read and write cycles, while independent non-volatile data resides in the highly STORE to QuantumTrap non-volatile elements initiated by reliable QuantumTrap cell. Data transfers from the SRAM to the software, device pin, or AutoStore on power down non-volatile elements (the STORE operation) takes place RECALL to SRAM initiated by software or power up automatically at power down. On power-up, data is restored to the SRAM (the RECALL operation) from the non-volatile Infinite read, write, and recall cycles memory. Both the STORE and RECALL operations are also 1 million STORE cycles to QuantumTrap available under software control. 20 year data retention For a complete list of related documentation, click here. Core V = 3.0 V to 3.6 V I/O V = 1.65 V to 1.95 V CC CCQ Industrial temperature 48-ball fine-pitch ball grid array (FBGA) package Pb-free and restriction of hazardous substances (RoHS) compliance 1, 2, 3 Logic Block Diagram V V VCCQ CC CAP Quatrum Trap 1024 X 1024 R A POWER 5 O CONTROL A STORE 6 W A 7 RECALL A D 8 STORE/RECALL A 9 E HSB CONTROL A STATIC RAM C 12 ARRAY A O 13 1024 X 1024 A D 14 SOFTWARE A E A - A 15 14 2 DETECT A R 16 DQ 0 DQ 1 DQ 2 DQ 3 I DQ 4 N DQ 5 P U DQ 6 T DQ 7 B COLUMN I/O U DQ 8 F DQ 9 F E OE DQ 10 COLUMN DEC R WE DQ S 11 DQ 12 DQ 13 CE DQ 14 BLE A A A A A A A 0 1 2 3 4 10 11 DQ 15 BHE Notes 1. Address A A for 8 configuration and Address A A for 16 configuration. 0 16 0 15 2. Data DQ DQ for 8 configuration and Data DQ DQ for 16 configuration. 0 7 0 15 3. BHE and BLE are applicable for 16 configuration only. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-53953 Rev. *K Revised November 6, 2014