Real-Time Ethernet Multiprotocol (REM) Switch Data Sheet fido5100/fido5200 FEATURES FUNCTIONAL BLOCK DIAGRAM 144-lead CSP BGA RoHS compliant package REM SWITCH 40C to +105C industrial temperature range rating TIMER HOST BUFFER 3.3 V input/output buffers CONTROL INTERFACE MEMORY UNIT IEEE 802.3, 10 Mbps/100 Mbps, half and full duplex, IPv6 and IPv4 communication INTERRUPT 2 independent Ethernet ports: 1 MII and 1 RMII interface per CONTROL port Support for all industrial protocols PORT 1 PORT 2 PROFINET Class B and Class C with fast startup (Version 2.3) EtherNet/IP with QuickConnect, CIP Sync, and CIP Motion Figure 1. Modbus TCP EtherCAT GENERAL DESCRIPTION Ethernet POWERLINK Host interface transfer rate: 32 bits per 28 ns The fido5100 and fido5200 (REM switch) are programmable Supports EtherCAT cycle times down to 12.5 s and IEEE 802.3 10 Mbps/100 Mbps Ethernet Internet Protocol PROFINET cycle times down to 31.25 s Version 6 (IPv6) and Internet Protocol Version 4 (IPv4) switches PI Net Load Class III capable that support virtually any Layer 2 or Layer 3 protocol. The DLR (supervisor and node, announce and beacon based), switches are personalized to support the desired protocol by MRPD, HSR, PRP, shared device, controller redundancy firmware that is downloaded from a host processor. IEEE 1588 Version 2 support: ordinary clock both peer to peer The firmware is contained in the real-time Ethernet multiprotocol and end to end transparent clocks, raw frames, and UDP (REM) switch driver and is downloaded at power-up. The REM 8 independent timer signals synchronized with an internal switch can be ready for network data operation in less than 4 ms to precision timer support fast startup and quick connect type network functionality. 4 independently programmable timer signals for timer The REM switch devices have the same signal assignments as capture events or timer output events defined in this data sheet. 4 timer signals create programmable periodic waveforms The fido5100 supports the following protocols: PROFINET real synchronized to the internal precision timer time (RT) and isochronous real time (IRT), EtherNet/IP with DCP, LLDP, DHCP, RSTP, VLAN, IGMP snooping support and without device level ring (DLR), Modbus TCP, and Forwarding table with aging and learning POWERLINK. Drive LEDs for link activity The fido5200 supports the following protocols: EtherCAT and APPLICATIONS all protocols defined for the fido5100. Industrial automation The REM switch is intended for use with a host processor. Process control Network operation is handled using the functions and services Managed Ethernet switch provided in the REM switch driver. The host processor can implement any protocol stack by integrating it with the REM switch driver. An example application is shown in Figure 11. The REM switches are available in a 144-ball chip scale package ball grid array (CSP BGA) package. Note that throughout this data sheet, multifunction pins, such as A02/ALE, are referred to either by the entire pin name or by a single function of the pin, for example, ALE, when only that function is relevant. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15833-001fido5100/fido5200 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Device Interfaces ........................................................................ 12 Functional Block Diagram .............................................................. 1 Internal Precision Timer ........................................................... 12 General Description ......................................................................... 1 Host Interface .............................................................................. 12 Revision History ............................................................................... 2 Ethernet Interface ....................................................................... 15 Specifications ..................................................................................... 3 Applications Information .............................................................. 17 REM Switch Characteristics ........................................................ 3 REM Switch Hardware .............................................................. 17 Timing SpecificationsNonmultiplexed Address Data Bus .. 3 Board Layout ............................................................................... 17 Timing SpecificationsMultiplexed Address Data Bus ......... 5 Design Considerations .............................................................. 17 Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 19 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 19 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 3/2020Rev. D to Rev. E 1/2019Rev. A to Rev. B Deleted Table 13 Renumbered Sequentially .............................. 18 Change to tAH Parameter, Table 2 .................................................... 3 Changes to Ordering Guide .......................................................... 19 1/2020Rev. C to Rev. D 8/2018Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Added Core Current Parameter and I/O Current Parameter, Table 1 ................................................................................................. 3 8/2019Rev. B to Rev. C Changes to tAS Parameter and tAH Parameter, Table 2 ................... 3 Change to Features Section, General Description Section, and Added Note 2 and Note 3, Table 2 Renumbered Sequentially ... 3 Figure 1 .............................................................................................. 1 Change to Power Dissipation Parameter, Table 4 ......................... 7 Changes to Figure 6 .......................................................................... 8 Change to Crystal Section and Figure 8 ...................................... 12 10/2017Revision 0: Initial Version Change to Figure 9 and Figure 10 ................................................ 16 Changes to Figure 11, REM Switch Hardware Section, and Power Section .................................................................................. 17 Changes to Table 13 ........................................................................ 18 Rev. E Page 2 of 19