Low Noise, Matched
a
Dual PNP Transistor
MAT03
FEATURES PIN CONNECTION
Dual Matched PNP Transistor
TO-78
Low Offset Voltage: 100 V Max
(H Suffix)
Low Noise: 1 nV/Hz @ 1 kHz Max
High Gain: 100 Min
High Gain Bandwidth: 190 MHz Typ
Tight Gain Matching: 3% Max
Excellent Logarithmic Conformance: r 0.3 typ
BE
GENERAL DESCRIPTION
Each transistor is individually tested to data sheet specifications.
The MAT03 dual monolithic PNP transistor offers excellent
Device performance is guaranteed at 25C and over the extended
parametric matching and high frequency performance. Low
industrial and military temperature ranges. To ensure the long-
noise characteristics (1 nV/Hz max @ 1 kHz), high bandwidth term stability of the matching parameters, internal protection
(190 MHz typical), and low offset voltage (100 V max), makes diodes across the base-emitter junction clamp any reverse base-
the MAT03 an excellent choice for demanding preamplifier appli- emitter junction potential. This prevents a base-emitter breakdown
cations. Tight current gain matching (3% max mismatch) and condition that can result in degradation of gain and matching
high current gain (100 min), over a wide range of collector cur- performance due to excessive breakdown current.
rent, makes the MAT03 an excellent choice for current mirrors.
A low value of bulk resistance (typically 0.3 ) also makes the
MAT03 an ideal component for applications requiring accurate
logarithmic conformance.
REV. C
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reliable. However, no responsibility is assumed by Analog Devices for its
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Fax: 781/326-8703 Analog Devices, Inc., 2002MAT03SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ T = 25C, unless otherwise noted.)
A
MAT03E MAT03F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
1
Current Gain h V = 0 V, 36 V
FE CB
I = 1 mA 100 165 80 165
C
I = 100 A 90 150 70 150
C
I = 10 A 80 120 60 120
C
2
Current Gain Matching Dh I = 100 A,V = 0 V 0.5 3 0.5 6 %
FE C CB
3
Offset Voltage V V = 0 V, I = 100 A 40 100 40 200 V
OS CB C
Offset Voltage Change V / V I = 100 A
OS CB C
vs. Collector Voltage V = 0 V 11 150 11 200 V
CB1
V = 36 V 11 150 11 200 V
CB2
Offset Voltage Change V / I V = 0 V 12 50 12 75 V
OS C CB
vs. Collector Current I = 10 A, I = 1 mA 12 50 12 75 V
C1 C2
Bulk Resistance r V = 0 V 0.3 0.75 0.3 0.75
BE CB
10 A I 1 mA 0.3 0.75 0.3 0.75
C
Offset Current I I = 100 A, V = 0 V 6 35 6 45 nA
OS C CB
Collector-Base
Leakage Current I V = 36 V = V 50 200 50 400 pA
CB0 CB MAX
4
Noise Voltage Density e I = 1 mA, V = 0
N C CB
f = 10 Hz 0.8 0.8 nV/Hz
O
f = 100 Hz 0.7 0.7 nV/Hz
O
f = 1 kHz 0.7 0.7 nV/Hz
O
f = 10 kHz 0.7 0.7 nV/Hz
O
Collector Saturation
Voltage V I = 1 mA, I = 100 A 0.025 0.1 0.025 0.1 V
CE(SAT) C B
(@ 40C T 85C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS A
MAT03E MAT03F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Current Gain h V = 0 V, 36 V
FE CB
I = 1 mA 70 120 60 120
C
I = 100 A 60 105 50 105
C
I = 10 A 5090 4090
C
Offset Voltage V I = 100 A, V = 0 V 30 135 30 265 V
OS C CB
5
Offset Voltage Drift TCV I = 100 A, V = 0 V 0.3 0.5 0.3 1.0 V/C
OS C CB
Offset Current I I = 100 A, V = 0 V 1085 10200 nA
OS C CB
Breakdown Voltage BV 36 36 V
CEO
NOTES
1
Current gain is measured at collector-base voltages (V ) swept from 0 to V at indicated collector current. Typicals are measured at V = 0 V.
CB MAX CB
100 ( I ) h (min )
B FE
2
Current gain matching ( h ) is defined as: h
FE FE = .
I
C
I
C1
KT
3
Offset voltage is defined as: V = V V , where V is the differential voltage for I = I : V = V V = In .
OS BE1 BE2 OS C1 C2 OS BE1 BE2
q
I
C2
4
Sample tested. Noise tested and specified as equivalent input voltage for each transistor.
5
Guaranteed by V test (TCV = V /T for V V ) where T = 298K for T = 25C.
OS OS OS OS BE A
Specifications subject to change without notice.
REV. C
2