CS8900A
Product Data Sheet
FEATURES
Crystal LAN Ethernet
Single-Chip IEEE 802.3 Ethernet Controller with
Controller
Direct ISA-Bus Interface
Maximum Current Consumption = 55 mA (5V
DESCRIPTION
Supply)
The CS8900A is a low-cost Ethernet LAN Controller op-
3V or 5V Operation
timized for the Industry Standard Architecture (ISA) bus
Industrial Temperature Range
and general purpose microcontroller busses. Its highly-
Comprehensive Suite of Software Drivers integrated design eliminates the need for costly external
Available
components required by other Ethernet controllers. The
CS8900A includes on-chip RAM, 10BASE-T transmit
Efficient PacketPage Architecture Operates in
I/O and Memory Space, and as DMA Slave
and receive filters, and a direct ISA-Bus interface with
24 mA Drivers.
Full Duplex Operation
In addition to high integration, the CS8900A offers a
On-Chip RAM Buffers Transmit and Receive
Frames broad range of performance features and configura-
tionoptions. Its unique PacketPage architecture
10BASE-T Port with Analog Filters, Provides:
automatically adapts to changing network traffic pat-
- Automatic Polarity Detection and Correction
terns and available system resources. The result is
AUI Port for 10BASE2, 10BASE5 and 10BASE-F
increased system efficiency.
Programmable Transmit Features:
The CS8900A is available in a 100-pin LQFP package
- Automatic Re-transmission on Collision
ideally suited for small form-factor, cost-sensitive Ether-
- Automatic Padding and CRC Generation
net applications. With the CS8900A, system engineers
can design a complete Ethernet circuit that occupies
Programmable Receive Features:
less than 1.5 square inches (10 sq. cm) of board space.
- Stream Transfer for Reduced CPU Overhead
- Auto-Switch Between DMA and On-Chip Memory
ORDERING INFORMATION
- Early Interrupts for Frame Pre-Processing
- Automatic Rejection of Erroneous Packets
CS8900A-CQZ 0 to 70 C 5V LQFP-100 Lead free
CS8900A-IQZ -40 to 85 C 5V LQFP-100 Lead free
EEPROM Support for Jumperless Configuration
CS8900A-CQ3Z 0 to 70 C 3.3V LQFP-100 Lead free
Boot PROM Support for Diskless Systems
CS8900A-IQ3Z -40 to 85 C 3.3V LQFP-100 Lead free
Boundary Scan and Loopback Test
LED Drivers for Link Status and LAN Activity
Standby and Suspend Sleep Modes
20 MHz
EEPROM
XTAL
CS8900A ISA Ethernet Controller
LED
Clock
10BASE-T
Control
RX Filters &
EEPROM
RAM
Receiver
Control
RJ-45 10BASE-T
10BASE-T
TX Filters &
Encoder/
Transmitter
Host
Decoder
Bus
&
Logic
PLL
AUI
Transmitter
Attachment
Unit
802.3 AUI
Memory
Interface
Collision
MAC
Boundary
Manager
(AUI)
Engine Power
AUI
Scan
Manager
Test Logic Receiver
DS271F6 JUN 15
Copyright Cirrus Logic, Inc. 1997-2015
(All Rights Reserved)
Host BusCS8900A
Crystal LAN Ethernet Controller
TABLE OF CONTENTS
1.0 INTRODUCTION ......................................................................................................................8
1.1 General Description ...........................................................................................................8
1.1.1 Direct ISA-Bus Interface .......................................................................................8
1.1.2 Integrated Memory ...............................................................................................8
1.1.3 802.3 Ethernet MAC Engine .................................................................................8
1.1.4 EEPROM Interface ...............................................................................................8
1.1.5 Complete Analog Front End .................................................................................8
1.2 System Applications ..........................................................................................................8
1.2.1 Motherboard LANs ...............................................................................................8
1.2.2 Ethernet Adapter Cards ........................................................................................9
1.3 Key Features and Benefits ..............................................................................................10
1.3.1 Very Low Cost ....................................................................................................10
1.3.2 High Performance ...............................................................................................10
1.3.3 Low Power and Low Noise .................................................................................10
1.3.4 Complete Support ...............................................................................................10
2.0 PIN DESCRIPTION .............................................................................................................12
3.0 FUNCTIONAL DESCRIPTION...............................................................................................17
3.1 Overview .........................................................................................................................17
3.1.1 Configuration ......................................................................................................17
3.1.2 Packet Transmission ..........................................................................................17
3.1.3 Packet Reception ...............................................................................................17
3.2 ISA Bus Interface ............................................................................................................18
3.2.1 Memory Mode Operation ....................................................................................18
3.2.2 I/O Mode Operation ............................................................................................18
3.2.3 Interrupt Request Signals ...................................................................................18
3.2.4 DMA Signals .......................................................................................................18
3.3 Reset and Initialization ....................................................................................................19
3.3.1 Reset ..................................................................................................................19
3.3.1.1 External Reset, or ISA Reset ...............................................................19
3.3.1.2 Power-Up Reset ..................................................................................19
3.3.1.3 Power-Down Reset ..............................................................................19
3.3.1.4 EEPROM Reset ...................................................................................19
3.3.1.5 Software Initiated Reset .......................................................................19
3.3.1.6 Hardware (HW) Standby or Suspend ..................................................19
3.3.1.7 Software (SW) Suspend ......................................................................19
3.3.2 Allowing Time for Reset Operation .....................................................................20
3.3.3 Bus Reset Considerations ..................................................................................20
3.3.4 Initialization .........................................................................................................20
3.4 Configurations with EEPROM .........................................................................................21
3.4.1 EEPROM Interface .............................................................................................21
3.4.2 EEPROM Memory Organization .........................................................................21
3.4.3 Reset Configuration Block ..................................................................................21
3.4.3.1 Reset Configuration Block Structure ....................................................22
3.4.3.2 Reset Configuration Block Header ......................................................22
3.4.3.3 Determining the EEPROM Type ..........................................................23
3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ..........23
3.4.3.5 Determining Number of Bytes in the Reset Configuration Block .........23
3.4.4 Groups of Configuration Data .............................................................................23
3.4.4.1 Group Header ......................................................................................23
3.4.5 Reset Configuration Block Checksum ................................................................24
3.4.6 EEPROM Example .............................................................................................24
3.4.7 EEPROM Read-out ............................................................................................24
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