PI6C557-05B PCIe 3.0 Clock Generator with 4 HCSL Outputs Features Description PCIe 3.0 c om pl a i nt T he PI6 C557- 05 B i s a s p r e a d s p e c t r u m clo ck ge ne r at or c om pl ia nt to PCI Express 3.0 a nd Et he r ne t r e q u i r e me nt s. T he d ev ic e i s u s e d P C Ie 3.0 Ph a s e jit t e r : 0.48p s R M S ( H ig h Fr e q. Ty p.) for PC or embedded systems to subst a nt ially reduce Elect romag net ic LV DS c om p at i ble out put s I nt e r fe r e n c e ( E M I ). Su p ply volt a ge of 3. 3V 5% T he PI6 C557- 05 B p r ov id e s fou r d i f fe r e nt ia l ( HCSL) or LV DS 25 M H z c r y s t a l or clo ck i n put f r e q u e n c y s p r e a d s p e c t r u m out put s. T he PI6 C557- 05 B i s c o n gfi u r e d t o s ele c t s pre a d a nd clo ck sele ct ion. Usi ng Pe r ic om s pat e nt e d Ph a se -L o cke d HCSL out put s , 0.7 V C u r r e nt mo d e d i f fe r e nt ia l p a i r L o o p ( PL L) t e ch n iq u e s , t he d ev ic e t a ke s a 25 M H z c r y s t a l i n put Jit t e r 4 0 p s c ycle - t o - c ycle (t y p) a nd p r o d u c e s fou r p a i r s of d i f fe r e nt ia l out put s ( HCSL) at 100MHz Sp r e a d of - 0. 5% , -1.0 % , -1. 5% , a nd no s p r e a d a nd 20 0M H z clo ck f r e que ncie s. It a l s o pr ov id e s s pr e a d s ele c t ion of - 0. 5% , -1.0 % , -1. 5% , a nd no s p r e a d . I nd u s t r ia l t e m p e r at u r e r a nge Sp r e a d By p a s s o pt io n ava i l a ble Sp r e a d a nd f r e q u e n c y s ele c t io n v ia ex t e r n a l pi n s Pa ck ag i ng: ( Pb -f r e e a nd G r e e n) 20 - pi n , 173 - m i l w id e T SSOP Pin Configuration Block Diagram VDD PD OE 1 2 VDDXD 20 CLK0 2 S0 19 CLK0 Spread 3 S 2:0 Spectrum/ SS Circuitry S1 3 18 CLK1 Output clock 4 S2 CLK0 17 CLK1 selection CLK0 5 X1 CLK1 16 GNDODA CLK1 PLL 6 X2 15 VDDODA CLK2 X1/CLK 25 MHz Crystal CLK2 7 PD crystal 14 CLK2 CLK3 Driver or clock CLK3 X2 8 OE 13 CLK2 2 Pulling R r(IREF) Capacitors 9 GNDXD 12 CLK3 GND 10 IREF 11 CLK3 All trademarks are property of their respective owners. www.diodes.com 3/21/17 17-0052 1PI6C557-05B Pin Description Pin Pin Name I/O Type Description 1 VDDXD Power Connect to a +3.3V source. 2 S0 Input Spread Spectrum Select pin 0. See Spred Spectrum Selec table. Internal pull-up resistor. 3 S1 Input Spread Spectrum Select pin 1. See Spred Spectrum Selec table. Internal pull-up resistor. 4 S2 Input Spread Spectrum Select pin 2. See Spred Spectrum Selec table. Internal pull-up resistor. 5 X1 Input Crystal connection. 6 X2 Output Crystal connection. 7 PD Input Power down. Internal pull-up resistor. 8 OE Input Output enable. Tri-states output (High=enable outputs) Low=disable outputs). Internal pull-up resister. 9 GND Power Connect to digital circuit ground. 10 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 11 CLK3 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 3. 12 CLK3 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 3. 13 CLK2 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 2. 14 CLK2 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 2. 15 VDDODA Power Connect to a +3.3V analog source. 16 GND Power Output and Analog circuit ground 17 CLK1 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 1. 18 CLK1 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 1. 19 CLK0 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 0. 20 CLK0 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 0. Table 2: Spread Selection Table S2 S1 S0 Spread % Spread Type Output Frequency 0 0 0 -0.5 Down 100 0 0 1 -1.0 Down 100 0 1 0 -1.5 Down 100 0 1 1 No Spread Not Applicable 100 1 0 0 -0.5 Down 200 1 0 1 -1.0 Down 200 1 1 0 -1.5 Down 200 1 1 1 No Spread Not Applicable 200 All trademarks are property of their respective owners. www.diodes.com 3/21/17 17-0052 2