PI6C557-05 PCIe 2.0 Clock Generator with 4 HCSL Outputs Description Product Features PCIe 2.0 complaint e PTh I6C557-05 is a spread spectrum clock generator compliant to PCI Express 2.0 and Ethernet requirements. The device is Phase jitter - 2.1ps RMS (typ) used for PC or embedded systems to substantially reduce Elec- LVDS compatible outputs tromagnetic Interference (EMI). Supply voltage of 3.3V 5% e PTh I6C557-05 provides four differential (HCSL) or LVDS 25MHz crystal or clock input frequency spread spectrum outputs. The PI6C557-05 is configured to select HCSL outputs, 0.7V Current mode differential pair spread and clock selection. Using Pericom s patented Phase- Jitter 40ps cycle-to-cycle (typ) Locked Loop (PLL) techniques, the device takes a 25MHz crys- tal input and produces four pairs of differential outputs (HCSL) Spread of -0.5%, -1.0%, -1.5%, and no spread at 100MHz and 200MHz clock frequencies. It also provides Industrial temperature range spread selection of -0.5%, -1.0%, -1.5%, and no spread. Spread Bypass option available Spread and frequency selection via external pins Packaging: (Pb-free and Green) 20-pin, 173-mil wide TSSOP Pin Configuration Block Diagram VDD PD OE 1 2 VDDXD 20 CLK0 2 S0 19 CLK0 Spread 3 S 2:0 Spectrum/ SS Circuitry S1 3 18 CLK1 Output clock 4 S2 CLK0 17 CLK1 selection CLK0 5 X1 CLK1 16 GNDODA CLK1 PLL 6 X2 15 VDDODA CLK2 X1/CLK 25 MHz Crystal CLK2 7 PD crystal 14 CLK2 CLK3 Driver or clock CLK3 X2 8 OE 13 CLK2 2 Pulling R r(IREF) Capacitors 9 GNDXD 12 CLK3 GND 10 IREF 11 CLK3 All trademarks are property of their respective owners. www.pericom.com P-0.1 04/29/11 11-0063 1PI6C557-05 PCIe 2.0 Clock Generator with 4 HCSL Outputs Pin Description Pin Pin Name I/O Type Description 1 VDDXD Power Connect to a +3.3V source. 2 S0 Input Spread Spectrum Select pin 0. See Spread Spectrum Selection table. Internal pull-up resistor. 3 S1 Input Spread Spectrum Select pin 1. See Spread Spectrum Selection table. Internal pull-up resistor. 4 S2 Input Spread Spectrum Select pin 2. See Spread Spectrum Selection table. Internal pull-up resistor. 5 X1 Input Crystal connection. 6 X2 Output Crystal connection. 7 PD Input Power down. Internal pull-up resistor. Output enable. Tri-states output (High=enable outputs) Low=disable outputs). Internal pull- 8 OE Input up resistor. 9 GND Power Connect to digital circuit ground. 10 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 11 CLK3 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 3. 12 CLK3 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 3. 13 CLK2 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 2. 14 CLK2 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 2. 15 VDDODA Power Connect to a +3.3V analog source. 16 GND Power Output and Analog circuit ground 17 CLK1 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 1. 18 CLK1 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 1. 19 CLK0 Output Selectable 100/200 MHz Spread Spectrum differential compliment output clock 0. 20 CLK0 Output Selectable 100/200 MHz Spread Spectrum differential true output clock 0. Table 2: Spread Selection Table S2 S1 S0 Spread % Spread Type Output Frequency 0 0 0 -0.5 Down 100 0 0 1 -1.0 Down 100 0 1 0 -1.5 Down 100 0 1 1 No Spread Not Applicable 100 1 0 0 -0.5 Down 200 1 0 1 -1.0 Down 200 1 1 0 -1.5 Down 200 1 1 1 No Spread Not Applicable 200 All trademarks are property of their respective owners. www.pericom.com P-0.1 04/29/11 11-0063 2