A product Line of Pb Diodes Incorporated Lead-free Green PI6CG33401C 3.3V Very-Low-Power 4-Output PCIe Clock Generator With On-Chip Termination Features Description 3.3V Supply Voltage e PTh I6CG33401C is a 4-output very-low-power PCIe Gen1/Gen2/ Crystal/CMOS Input: 25MHz Gen3/Gen4/Gen 5 clock generator. It uses 25MHz crystal or CMOS Four Differential Low Power HCSL Outputs with On-Chip reference as an input to generate the 100MHz low-power differ - Termination ential HCSL outputs with on-chip terminations. The on-chip ter - Default Z = 100 OUT mination can save 16 external resistors and make layout easier. An additional buffered reference output is provided to serve as a Individual Output Enable low-noise reference for other circuitry. Reference CMOS Output Programmable Slew Rate and Output Amplitude for Each It uses Diodes proprietary PLL design to achieve very-low Output jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen5 require- Differential Outputs Blocked until PLL is Locked ments. It also provides various options such as different slew rate Selectable 0%, -0.25%, or -0.5% Spread on Differential Outputs and amplitude through SMBUS, so users can configure the de - vice easily to get the optimized performance for their individual Strapping pins or SMBus for Configuration boards. The device also supports selectable spread-spectrum Differential Output-To-Output Skew <50ps options to reduce EMI for various applications. Very-Low Jitter Outputs Differential Cycle-To-Cycle Jitter <50ps PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Compliant Block Diagram CMOS REFOUT Phase Jitter < 0.3ps RMS, SSC off REFOUT OE 3:0 <1.5ps RMS, SSC on Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Q3 XTAL IN/CLK OSC PLL For automotive applications requiring specic cfi hange control XTAL OUT SS Q2 (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please SCLK Q1 SDATA contact us or your local Diodes representative. SADR CTRL SS SEL TRI Q0 A product Line of Diodes Incorporated PI6CG33401C Pin Configuration 32 31 30 29 28 27 26 25 1 GND OE2 24 XTAL IN/CLK 2 23 Q2- XTAL OUT 3 22 Q2+ VDD OSC 4 21 VDDA GND V DD REFOUT 5 20 GNDA SADR/REFOUT Q1- 6 19 GND REF 7 18 Q1+ GND DIG 8 17 OE1 9 10 11 12 13 14 15 16 Pin Description Pin Pin Name Type Description 1, 15, 26, 30 GND Power Ground pin 2 XTAL IN/CLK Input Crystal input or CMOS reference input 3 XTAL OUT Output Crystal output 4 V OSC Power Power supply for oscillator circuitry, nominal 3.3V DD 5 V REFOUT Power Power supply for buffered CMOS output DD Input/ Latch to select SMBus Address or LVCMOS REFOUT. 6 SADR/REFOUT CMOS Output This pin has an internal pulldown. 7 GND REF Power Ground for REFOUT 8 GND DIG Power Ground for digital circuitry 9 V DIG Power Power supply for digital circuitry, nominal 3.3V DD 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 11 SDATA CMOS SMBUS Data line, 3.3V tolerant Output Active low input for enabling Q0 pair. This pin has an internal pull-down. 12 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 16, 25 V Power Power supply for differential outputs DDO www.diodes.com January 2020 PI6CG33401C 2 Diodes Incorporated Document Number DS42293 Rev 3-2 V DIG DD SS SEL TRI SCLK PD SDATA GND OE0 OE3 Q0+ Q3- Q0- Q3+ GND GND V O DD V DDO