A product Line of Pb Diodes Incorporated Lead-free Green PI6CG33801C 3.3V Very Low Power 8-Output PCIe Clock Generator With On-chip Termination Features Description 3.3V Supply Voltage e PTh I6CG33801C is an 8-output very low power PCIe Gen1/Gen2/ Crystal/CMOS input: 25 MHz Gen3/ Gen4/ Gen 5 clock generator. It uses 25MHz crystal or CMOS reference as an input to generate the 100MHz low power differ - 8 differential low power HCSL outputs with on-chip termination ential HCSL outputs with on-chip terminations. The on-chip ter - mination can save 32 external resistors and make layout easier. Default Z = 100 OUT An additional buffered reference output is provided to serve as a Individual output enable low noise reference for other circuitry. Reference CMOS output Programmable slew rate and output amplitude for each output It uses Diodes proprietary PLL design to achieve very low Differential outputs blocked until PLL is locked jitter that meets PCIe Gen1/Gen2/Gen3/Gen4/Gen 5 require- ments. It also provides various options such as different slew rate Selectable 0%, -0.25% or -0.5% spread on differential outputs and amplitude through SMBUS so that users can configure the Strapping pins or SMBus for configuration device easily to get the optimized performance for their individ- Differential Output-To-Output Skew <60ps ual boards. The device also supports selectable spread-spectrum Very-Low Jitter Outputs options to reduce EMI for various applications. Differential Cycle-To-Cycle Jitter <50ps PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Compliant CMOS REFOUT Phase Jitter Block Diagram < 0.3ps RMS, SSC off <1.5ps RMS, SSC on REFOUT OE 7:0 Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Q7 Halogen and Antimony Free. Green Device (Note 3) Q6 For automotive applications requiring specic cfi hange control XTAL IN/CLK OSC PLL (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, XTAL OUT SS Q5 and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. SCLK Q4 SDATA A product Line of Diodes Incorporated PI6CG33801C Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 1 Q5- SS SEL TRI 36 2 Q5+ GND XTAL 35 3 OE4 XTAL IN/CLK 34 4 Q4- XTAL OUT 33 V 5 32 Q4+ DD OSC V 6 31 VDDO DD REFOUT GND SADR/REFOUT 7 30 VDDA GND REFOUT 8 29 GNDA 9 OE3 GND DIG 28 10 27 Q3- SCLK 11 SDATA 26 Q3+ 12 V 25 OE2 DD DIG 13 14 15 16 17 18 19 20 21 22 23 24 Pin Description Pin Pin Name Type Description Latched select input to select spread spectrum amount at initial power up. 1 = -0.5% spread, M = Spread O, 0 = Sff pread Off. This pin has both in - 1 SS SEL TRI Input Tri-level ternal pull-up and pull-down. Refer to SMBUS byte 1 bit 4, 3 = 01 to get -0.25% spread. 2 GND XTAL Power Ground for oscillator circuit 3 XTAL IN/CLK Input Crystal input or CMOS reference input 4 XTAL OUT Output Crystal output 5 V OSC Power Power supply for oscillator circuitry, nominal 3.3V DD 6 V REFOUT Power Power supply for buffered CMOS output DD Input/ Latch to select SMBus Address or LVCMOS REFOUT. 7 SADR/REFOUT CMOS Output This pin has an internal pull-down 8 GND REFOUT Power Ground for REFOUT 9 GND DIG Power Ground for digital circuitry 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 11 SDATA CMOS SMBUS Data line, 3.3V tolerant Output 12 V DIG Power Power supply for digital circuitry, nominal 3.3V DD 13, 21, 31, V Power Power supply for differential outputs DDO 39, 47 Active low input for enabling Q0 pair. This pin has an internal pull-down. 14 OE0 Input CMOS 1 =disable outputs, 0 = enable outputs 15 Q0+ Output HCSL Differential true clock output www.diodes.com January 2020 PI6CG33801C 2 Diodes Incorporated Document Number DS42297 Rev 3-2 V O DD PD OE0 V O DD Q0+ OE7 Q0- Q7- OE1 Q7+ Q1+ OE6 Q1- Q6- VDD Q6+ GND V O DD V O DD GND V Q2+ DD OE5 Q2-