PI6C20800B
PI6CXG06F62a
FlexOut Ultra Low Jitter Clock Generator
Features Description
Ultra low jitter 156.25MHz clock generator <0.1ps max (12k e PTh I6CXG06F62a is part of Pericom's FlexOut clock genera -
to 20MHz) in LVPECL configuration
tor family. FlexOut generators combine a low jitter high per-
formance clock generator along with fanout capabilities. It also
6 differential outputs with 2 banks
integrates a unique feature with user configurable output signal -
User configurable output signaling standard for each bank:
ing standards on per bank basis which provide great flexibility
LVDS or LVPECL or HCSL
to users. This device is ideal for systems that need to distribute
Separate supply voltages for customizable output levels
low jitter clock signals to multiple destinations.
Low skew between outputs within banks (<40ps)
2.5V / 3.3V power supply
Applications
Industrial temperature support
Networking systems including switches and routers
LQFP-48 package
High frequency backplane based computing and telecom
platforms
Block Diagram Pin Configuration (48-Pin LQFP)
NC
1 36 VDDO
OPMODEA[1:0]
GND 2 35
OPMODEA0
QA[0:2]
GND
3 34 OPMODEA1
3
NC
4 33
QA2
NC
5 32 nQA2
49 GND Pad
NC 6 31
QB0
OPMODEB[1:0]
NC 7 30 nQB0
Embedded
8 29
NC OPMODEB1
QB[0:2]
Clock Source
NC
9 28 OPMODEB0
3
NC
10 27
VDDO
IREF
NC
11 26 QB1
NC 12 25
nQB1
PI6CXG06F62a Rev B 11/03/15
15-0135 1
NC 48 NC
13
47
14 NC
SOURCE_OE
46
VDD_INTCLK 15 NC
45
VDD_INTCLK 16
NC
VDD 44
17 NC
43
18 Reserve
NC
GND 42
19
VEE
41
IREF 20
VDD_SEL0
40
GND 21 QA0
39
nQB2
22 nQA0
QB2 38 QA1
23
37
24
nQA1
VDDOPI6CXG06F62a
FlexOut Ultra Low Jitter Clock Generator
Pinout Table
Pin # Pin Name Type Description
2, 3, 19, 21 GND Power Connect to Ground
14 SOURCE_OE Input Control of embedded clock source ON/ OFF
15, 16 VDD_INTCLK Power Voltage supply for embedded clock source
17 VDD Power Power supply for core
Reference current for HCSL output tuning. Typically
20 IREF Output
connected with external 475 resistor to GND
nQB2
Bank B differential output pair. Pin selectable
22, 23 Output
LVPECL/LVDS/HCSL interface levels.
QB2
24, 27, 36 VDDO Power Power supply for output buffers
nQB1
Bank B differential output pair. Pin selectable
25, 26 Output
LVPECL/LVDS/HCSL interface levels.
QB1
28 OPMODEB0 Input Bank B output selection pin
29 OPMODEB1 Input Bank B output selection pin
nQB0
Bank B differential output pair. Pin selectable
30, 31 Output
LVPECL/LVDS/HCSL interface levels.
QB0
nQA2
Bank A differential output pair. Pin selectable
32, 33 Output
LVPECL/LVDS/HCSL interface levels.
QA2
34 OPMODEA1 Input Bank A output selection pin
35 OPMODEA0 Input Bank A output selection pin
nQA1
Bank A differential output pair. Pin selectable
37, 38 Output
LVPECL/LVDS/HCSL interface levels.
QA1
nQA0
Bank A differential output pair. Pin selectable
39, 40 Output
LVPECL/LVDS/HCSL interface levels.
QA0
41 VDD_SEL0 Power Connect to power supply, tie high
42 VEE Power Connect to Negative power supply
Embedded source debug pin. To be left open and not
43 Reserve Output (Do not connect)
connected in application.
49 GND Pad Power Exposed pad to be connected to Ground
1, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 18, 44, NC - No connect
45, 46, 47, 48
PI6CXG06F62a Rev B 11/03/15
15-0135 2