PI6LC4830
TM
HiFlex Network Clock Generator
Features Description
3.3V supply voltage
e PTh I6LC4830 is an LC VCO based low phase noise design
intended for the most demanding PCIe 2.0 applications. Use
3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function
of the ultra-low noise LC VCO allows for much greater noise
1 LVCMOS 100/50MHz selectable
margins than traditional solutions. This is ideal for noisy envi -
25MHz crystal or differential input
ronments.
Low 1ps RMS max integrated phase noise design
PLL Bypass mode for test
Pin Configuration
32 lead 5x5mm TQFN package
32 31 30 29 28 27 26 25
PLL_Byps 1
24
QA1+
2
REF_OUT_OE
23
QA1-
3
QB_OE
22
VDD_Out
4
QB_DIV2
21
QA2+
GND
5
VDD_PLL
20
QA2-
6
IN+
19
GND
7
IN-
18
QA_CMOS
VDD_REF_Out
8
17
VDD_OutA_SE
16
9 10 11 12 13 14 15
Block Diagram
REF_OUT_OE
PLL_Byps
REF_OUT
QA0:QA2
IN_SEL
100MHz
HCSL Outputs
OSC
QA_CMOS
PLL /R
IN+
IN-
QA_OE
QB_CMOS
/2
QB_DIV2
QB_OE
PI6LC4830 Rev B 08/17/12
12-0238
1
REF_OUT+ VDDA_PLL
REF_OUT- VDD
QA_OE
VDD_Out
X1
IREF
X2
VDD_OSC
QA0+
VDD_OutB_SE QA0-
GND
QB_CMOS
IN_SELPI6LC4830
TM
HiFlex Network Clock Generator
Pin Description
Pin Number Pin Name Type Description
20, 21, 23, 24, QA0+, QA0-, QA1+,
Output (HCSL) 100MHz HCSL Outputs
26, 27 QA1-, QA2+, QA2-
25MHz LVPECL output from fundamental oscillator
9, 10 REF_Out+, REF_Out- Output (LVPECL)
core
12 X1 Input Crystal input pin
13 X2 Output Oscillator output pin
6, 7 IN+, IN- Input (Differential) HCSL/LVPECL/LVDS inputs
Low selects X1 and X2, High selects In+, In-. Internal
11 IN_SEL Input (LVCMOS)
pull up is 100k Ohms
If Low, output buffers are switched to the PLL. If High,
1 PLL_Byps Input (LVCMOS) output buffers are switched to the input mux. Internal
100K-Ohm pulldown.
Low enables outputs, High selects high impedance
30, 3 QA_OE, QB_OE Input (LVCMOS)
mode. Internal 100K-Ohm pulldown
14 Power Power for xtal Osc core
V _OSC
DD
5 Power Power for digital portion of PLL circuitry
V _PLL
DD
22, 29 Power Power for output buffers
V _Out
DD
32 Power Power for analog core of PLL
V _PLL
DDA
19, 25 GND Power Ground
18 QA_CMOS Output (LVCMOS) 100MHz LVCMOS Output
16 QB_CMOS Output (LVCMOS) 100/50MHz Selectable LVCMOS Output
17 V _OutA_SE Power Bank A LVCMOS Power
DD
15 Power Bank B LVCMOS Power
V _OutB_SE
DD
High selects 50MHz, Low selects 100MHz. Internal
4 QB_DIV2 Input (LVCMOS)
100K-Ohm pull-up
External resistor connection for internal current refer-
28 I Output
REF
ence
8 V _REF_OUT Power Power for reference output
DD
Low enables outputs, High selects high impedance
2 REF_OUT_OE Input (LVCMOS)
mode. Internal 100K-Ohm pull-down.
31 V Power Power for Core
DD
PI6LC4830 Rev B 08/17/12
12-0238
2