PI6LC48P03
3-Output LVPECL Networking Clock Generator
Features Description
Three differential LVPECL output pairs e PTh I6LC48P03 is a 3-output LVPECL synthesizer optimized to
generate Ethernet reference clock frequencies and is a member
Selectable crystal oscillator interface or LVCMOS/LVTTL
of Pericoms HiFlex family of high performance clock solutions.
single-ended clock input
Using a 31.25MHz or 26.041666MHz crystal, the most popular
Supports the following output frequencies: 125MHz,
Ethernet frequencies can be generated based on the settings of 4
156.25MHz, 312.5MHz, 625MHz
frequency select pins.
RMS phase jitter @ 156.25MHz, using a 31.25MHz or
e PTh I6LC48P03 uses Pericoms proprietary low phase noise
26.041666MHz crystal (12kHz 20MHz): 0.3ps (typical)
PLL technology to achieve ultra low phase jitter, so it is ideal for
Full 3.3V or 2.5V supply modes
Ethernet interface in all kind of systems.
PI6C20800B
Commercial and industrial ambient operating temperature
Available in lead-free package: 24-TSSOP
Applications
Networking systems
Block Diagram
NA_SEL[0:1]
OEA
CLKA
/A
CLKA#
XTAL_IN
OEB
OSC
PFD VCO
XTAL_OUT
CLKB0
/B
CLKB0#
Ref_IN
CLKB1
M
CLKB1#
IN_SEL#
PLL_ByPass#
FBN
NB_SEL[0:1]
M_reset
www.pericom.com PI6LC48P03 Rev. C 5/7/2015
15-0059 1PI6LC48P03
3-Output LVPECL Networking Clock Generator
Pin Configuration
NB_SEL0 24
1 NB_SEL1
PLL_ByPass# 23 VDDOB
2
M_reset 22
3 CLKB0
VDDOA 4 21 CLKB0#
CLKA 5 20 CLKB1
CLKA# 6 19 CLKB1#
18
OEB 7 IN_SEL#
17
OEA 8 Ref_IN
FBN 9 16 XTAL_IN
15
VDDA 10 XTAL_OUT
VDD 11 14 GND
13
NA_SEL0 12 NA_SEL1
Pinout Table
Pin No. Pin Name I/O Type Description
1 NB_SEL0 Input Pull-down Bank B Output Divider Select
2 PLL_ByPass# Input Pull-up Active Low PLL Bypass
Master Reset. When HIGH, CLKx goes to low and CLKx# goes to
3 M_reset Input Pull-down
high; When LOW outputs are enabled.
4 VDDOA Power Bank A Output Power Supply
5, 6 CLKA, CLKA# Output Bank A LVPECL Output Clock
7 OEB Input Pull-up Bank B Output Enable. When LOW, output is differential low.
8 OEA Input Pull-up Bank A Output Enable. When LOW, output is differential low.
9 FBN Input Pull-down Feedback Divider Select
10 VDDA Power Analog Power Supply
11 VDD Power Core Power Supply
12 NA_SEL0 Input Pull-up Bank A Output Divider Select
13 NA_SEL1 Input Pull-down Bank A Output Divider Select
14 GND Ground Ground
XTAL_OUT,
15, 16 Crystal Crystal Input and Output
XTAL_IN
17 Ref_IN Input Pull-down CMOS Reference Clock Input
When HIGH, Crystal is selected; When LOW, reference input is
18 IN_SEL# Input Pull-up
selected.
19, 20 CLKB1#, CLKB1 Output Bank B LVPECL Output Clock 1
21, 22 CLKB0#, CLKB0 Output Bank B LVPECL Output Clock 0
23 VDDOB Power Bank B Output Power Supply
24 NB_SEL1 Input Pull-up Bank B Output Divider Select
www.pericom.com PI6LC48P03 Rev. C 5/7/2015
15-0059 2