PI6LC48P0401 4-Output LVPECL Networking Clock Generator Features Description Four differential LVPECL output pairs e PTh I6LC48P0401 is a 4-output LVPECL synthesizer opti - mized to generate Ethernet reference clock frequencies and is a Selectable crystal oscillator interface or LVCMOS/LVTTL member of Pericoms HiFlex family of high performance clock single-ended clock input solutions. Using a 25MHz crystal, the following frequencies can Supports the following output frequencies: 156.25MHz, be generated based on the settings of 2 frequency select pins 125MHz, 62.5MHz (N SEL 1:0 ): 156.25MHz, 125MHz, 62.5MHz. RMS phase jitter 156.25MHz, using a 25MHz crystal e PTh I6LC48P0401 uses Pericoms proprietary low phase noise (1.875MHz 20MHz): 0.23ps (typical) VCO technology and can achieve less than 1ps typical rms RMS phase jitter 156.25MHz, using a 25MHz crystal phase jitter, so it is ideal for Ethernet interface in all kind of (12kHz 20MHz): 0.28ps (typical) systems. Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free packages Applications Networking systems Block Diagram 2 N SEL 1:0 PLL Bypass CLK0 XTAL IN CLK0 OSC XTAL OUT N SEL 1:0 CLK1 0 0 4 Phase VCO CLK1 0 1 5 Detector Ref IN 1 0 10 1 1 not used CLK2 CLK2 IN SEL M = 25 (fixed) CLK3 CLK3 M reset www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 14-0203 1PI6LC48P0401 4-Output LVPECL Networking Clock Generator Pin Configuration CLK1 24 1 CLK2 CLK1 23 CLK2 2 V 22 DDO 3 V DDO 21 CLK0 4 CLK3 20 CLK0 5 CLK3 19 M reset 6 GND 18 PLL Bypass 7 V DD 17 NC 8 IN SEL 16 VDDA 9 Ref IN 15 N SEL0 10 GND 14 VDD 11 XTAL IN 13 N SEL1 12 XTAL OUT Pinout Table Pin No. Pin Name I/O Type Description 1, 2 CLK1 , CLK1 Output LVPECL Output Clock 1 3, 22 Power Output supply pins V DDO 4, 5 CLK0, CLK0 Output LVPECL Output Clock 0 Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs 6 M reset Input Pulldown nQx to go high. When logic LOW, the internal dividers and outputs are enabled. Selects either the PLL or the active input reference to be routed to the 7 PLL Bypass Input Pulldown output dividers. When LOW, selects PLL (PLL enable). When HIGH, selects the reference clock (PLL bypass). 8 NC Not connected 9 V Power Analog power supply DDA 10, N SEL0, Input Pulldown Frequency select pins 12 N SEL1 11, 18 Power Core power supply V DD 13, XTAL OUT, Output / Parallel resonant crystal interface. XTAL OUT is the output, and 14 XTAL IN Input XTAL IN is the input. 15, 19 GND Power Ground 16 Ref IN Input Pulldown CMOS reference clock input Selects between the single-ended Ref IN or crystal interface as the 17 IN SEL Input Pulldown PLL reference source. When HIGH, selects Ref IN. When LOW selects XTAL inputs. 20, 21 CLK3 , CLK3 Output LVPECL Output Clock 3 23, 24 CLK2, CLK2 Output LVPECL Output Clock 2 www.pericom.com PI6LC48P0401 Rev.D 11/7/2014 14-0203 2