PI6LC48S25BZBBIE Diodes Incorporated

PI6LC4820 TM HiFlex Ethernet Network Clock Generator Features Description 3.3V supply voltage e PTh I6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes Crystal input: 25 MHz a 25Mhz crystal input, while the PLL loop is used to generate Differential input: 25MHz, 156.25 MHz the 156.25MHz outputs. An additional buffered crystal oscilla - Output frequencies of 312.5, 156.25, 125MHz supported tor output is provided to serve as a low noise reference for other 9 LVPECL or LVDS bank selectable outputs circuitry. Low 1ps max integrated phase noise design For Ethernet applications other than 10GbE, programmable (12kHz to 20MHz) dividers allow for simultaneous output of 312.5, 156.25, and 125MHz. Optional xtal or clock input selection PLL Bypass mode for test Power supply noise rejection: -50 dBc typical 156.25 MHz Packaging (Pb-free & Green): 48-lead 77mm TQFN Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 1 36 V FS0 DD QA 2 QA0+ X1 35 3 QA0- X2 34 V 4 33 QA1+ DD OSC 5 32 QA1- IN SEL 6 QA2+ PLL BYPS 31 GND GND 7 30 QA2- 8 QA3+ FS1 29 9 QA3- QC Mode 28 10 27 QA4+ V DDA 11 GND 26 QA4- 12 V 25 V DD PLL DD QA 13 14 15 16 17 18 19 20 21 22 23 24 PI6LC4820 Rev D 11/13/13 13-0167 1 GND IN SE FS B IN+ GND IN- FS A QB Mode GND QA Mode0 FS C QB2+ QA Mode1 QB2- V QB1+ DD QB1- GND QB0+ QC- QB0- QC+ V DD QB V DD QCPI6LC4820 TM HiFlex Ethernet Network Clock Generator Block Diagram FS A PLL BYPS V DD V DD PLL FS0 V IN SEL DD OSC V QA Mode0 DD QA X1 QA0+ SaRonix-eCera Crystal 0 QA0- Oscillator GC25000-76B QA1+ 11 X2 QA1- F VCO QA2+ 0/NC LC VCO AA CHARGE/ CMOS NC M PFD QA2- IN SE QA3+ IN+ QA3- 1 DIFF. QA4+ IN- QA4- N QA Mode1 V DD QB QB Mode QB0+ QB0- 11 QB1+ QB1- POR BB 0/NC QB2+ QB2- V QC 11 DD QC+ NNCC QC- 00 CC QC Mode V DD QC FS1 FS B FS C PI6LC4820 Rev D 11/13/13 13-0167 2