5962-8687519XA E2v

REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline to the drawing. Change to parameter tWHAX of 89-10-30 Michael A. Frye table I. Editorial change throughout. B Changes in accordance with NOR 5962-R004-91 91-09-20 Michael A. Frye C Redrawn with changes. Added device types 19 through 22. Added 93-04-28 Michael A. Frye vendor CAGE 65786 for device types 19 and 20.. Added vendor CAGE 61772 for devices 21 and 22. Corrected errors to Table I. Added pin 1 reference to case outline U. Editorial changes throughout. D Boilerplate update, part of 5 year review. ksr 06-08-08 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison DEFENSE SUPPLY CENTER COLUMBUS CHECKED BY COLUMBUS, OHIO 43218-3990 STANDARD 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86875 01 X A Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Access time 01 1K x 8 bit dual port CMOS SRAM (Master) 90 ns 02 1K x 8 bit dual port CMOS SRAM (Master) 70 ns 03 1K x 8 bit dual port CMOS SRAM (Master) 55 ns 04 1K x 8 bit dual port CMOS SRAM (Master) 45 ns 05 1K x 8 bit dual port CMOS SRAM (Master) 90 ns (data retention) 06 1K x 8 bit dual port CMOS SRAM (Master) 70 ns (data retention) 07 1K x 8 bit dual port CMOS SRAM (Master) 55 ns (data retention) 08 1K x 8 bit dual port CMOS SRAM (Master) 45 ns (data retention) 09 1K x 8 bit dual port CMOS SRAM (Slave) 90 ns 10 1K x 8 bit dual port CMOS SRAM (Slave) 70 ns 11 1K x 8 bit dual port CMOS SRAM (Slave) 55 ns 12 1K x 8 bit dual port CMOS SRAM (Slave) 45 ns 13 1K x 8 bit dual port CMOS SRAM (Slave) 90 ns (data retention) 14 1K x 8 bit dual port CMOS SRAM (Slave) 70 ns (data retention) 15 1K x 8 bit dual port CMOS SRAM (Slave) 55 ns (data retention) 16 1K x 8 bit dual port CMOS SRAM (Slave) 45 ns (data retention) 17 1K x 8 bit dual port CMOS SRAM (Master) 35 ns 18 1K x 8 bit dual port CMOS SRAM (Slave) 35 ns 19 1K x 8 bit dual port CMOS SRAM (Master) 35 ns 20 1K x 8 bit dual port CMOS SRAM (Slave) 35 ns 21 1K x 8 bit dual port CMOS SRAM (Master) 35 ns (data retention) 22 1K x 8 bit dual port CMOS SRAM (Slave) 35 ns (data retention) 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T48 or CDIP2-T48 48 dual-in-line Y See figure 1 48 square leadless chip carrier Z CQCC1-N52 52 square leadless chip carrier U See figure 1 48 flat pack 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1/ Generic numbers are listed on the Standardized Military Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. SIZE STANDARD 5962-86875 A MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 D 2 DSCC FORM 2234 APR 97