X-On Electronics has gained recognition as a prominent supplier of GS81302DT38GE-400 SRAM across the USA, India, Europe, Australia, and various other global locations. GS81302DT38GE-400 SRAM are a product manufactured by GSI Technology. We provide cost-effective solutions for SRAM, ensuring timely deliveries around the world.

GS81302DT38GE-400 GSI Technology

GS81302DT38GE-400 electronic component of GSI Technology
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Part No.GS81302DT38GE-400
Manufacturer: GSI Technology
Category: SRAM
Description: SRAM Chip Sync Dual 1.8V 144M-Bit 4M x 36 0.45ns 165-Pin FBGA
Datasheet: GS81302DT38GE-400 Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
105: USD 191.0465 ea
Line Total: USD 20059.88 
Availability - 0
MOQ: 105  Multiples: 105
Pack Size: 105
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0
Ship by Mon. 30 Dec to Fri. 03 Jan
MOQ : 105
Multiples : 105
105 : USD 191.0465

   
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We are delighted to provide the GS81302DT38GE-400 from our SRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the GS81302DT38GE-400 and other electronic components in the SRAM category and beyond.

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GS81302DT06/11/20/38E-500/450/400/350 500 MHz350 MHz 165-Bump BGA 144Mb SigmaQuad-II+ 1.8 V V Commercial Temp DD Burst of 4 SRAM Industrial Temp 1.8 V or 1.5 V I/O are just one element in a family of low power, low voltage Features HSTL I/O SRAMs designed to operate at the speeds needed to 2.5 Clock Latency implement economical high performance networking systems. Simultaneous Read and Write SigmaQuad Interface JEDEC-standard pinout and package Dual Double Data Rate interface Clocking and Addressing Schemes Byte Write controls sampled at data-in time Burst of 4 Read and Write The GS81302DT06/11/20/38E SigmaQuad-II+ SRAMs are Dual-Range On-Die Termination (ODT) on Data (D), Byte synchronous devices. They employ two input register clock Write (BW), and Clock (K, K) intputs inputs, K and K. K and K are independent single-ended clock 1.8 V +100/100 mV core power supply inputs, not differential inputs to a single differential clock input 1.5 V or 1.8 V HSTL Interface buffer. Pipelined read operation Fully coherent read and write pipelines Each internal read and write operation in a SigmaQuad-II+ B4 ZQ pin for programmable output drive strength RAM is four times wider than the device I/O bus. An input Data Valid Pin (QVLD) Support data bus de-multiplexer is used to accumulate incoming data IEEE 1149.1 JTAG-compliant Boundary Scan before it is simultaneously written to the memory array. An 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package output data multiplexer is used to capture the data produced RoHS-compliant 165-bump BGA package available from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II+ B4 RAM is always two address pins SigmaQuad Family Overview less than the advertised index depth (e.g., the 16M x 8 has a The GS81302DT06/11/20/38E are built in compliance with 4M addressable index). the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302DT06/11/20/38E SigmaQuad SRAMs Parameter Synopsis -500 -450 -400 -350 tKHKH 2.0 ns 2.2 ns 2.5 ns 2.86 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.02c 8/2017 1/31 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS81302DT06/11/20/38E-500/450/400/350 4M x 36 SigmaQuad-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA A CQ SA W BW2 K BW1 R SA SA CQ (288Mb) B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 V SA NC SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 2 11 x 15 Bump BGA15 x 17 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 2. Pin A2 is the expansion address. Rev: 1.02c 8/2017 2/31 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
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