GS8160E18/32/36DGT-400/375/333/250/200/150 400 MHz150 MHz 100-Pin TQFP 1M x 18, 512K x 32, 512K x 36 2.5 V or 3.3 V V Commercial Temp DD 18Mb Sync Burst SRAMs Industrial Temp 2.5 V or 3.3 V I/O interleave order with the Linear Burst Order (LBO) input. The Features Burst function need not be used. New addresses can be loaded FT pin for user-configurable flow through or pipeline on every cycle with no degradation of chip performance. operation Dual Cycle Deselect (DCD) operation Flow Through/Pipeline Reads 2.5 V or 3.3 V +10%/10% core power supply The function of the Data Output register can be controlled by 2.5 V or 3.3 V I/O supply the user via the FT mode pin (Pin 14). Holding the FT mode LBO pin for Linear or Interleaved Burst mode pin low places the RAM in Flow Through mode, causing Internal input resistors on mode pins allow floating mode pins output data to bypass the Data Output Register. Holding FT Default to Interleaved Pipeline mode high places the RAM in Pipeline mode, activating the rising- Byte Write (BW) and/or Global Write (GW) operation edge-triggered Data Output Register. Internal self-timed write cycle DCD Pipelined Reads Automatic power-down for portable applications The GS8160E18/32/36DGT is a DCD (Dual Cycle Deselect) RoHS-compliant 100-lead TQFP package available pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable Functional Description commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin Applications turning off their outputs just after the second rising edge of The GS8160E18/32/36DGT is an 18,874,368-bit high clock. performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Byte Write and Global Write Cache applications supporting high performance CPUs, the Byte write operation is performed by using Byte Write enable device now finds application in synchronous SRAM (BW) input combined with one or more individual byte write applications, ranging from DSP main store to networking chip signals (Bx). In addition, Global Write (GW) is available for set support. writing all bytes at one time, regardless of the Byte Write control inputs. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst Sleep Mode control inputs (ADSP, ADSC, ADV), and write control inputs Low power (Sleep mode) is attained through the assertion (Bx, BW, GW) are synchronous and are controlled by a (High) of the ZZ signal, or by stopping the clock (CK). positive-edge-triggered clock input (CK). Output enable (G) Memory data is retained during Sleep mode. and power down control (ZZ) are asynchronous inputs. Burst Core and Interface Voltages cycles can be initiated with either ADSP or ADSC inputs. In The GS8160E18/32/36DGT operates on a 3.3 V or 2.5 V Burst mode, subsequent burst addresses are generated power supply. All input are 3.3 V and 2.5 V compatible. internally and are controlled by ADV. The burst address Separate output power (V ) pins are used to decouple counter may be configured to count in either linear or DDQ output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -400 -375 -333 -250 -200 -150 Unit t 2.5 2.5 2.5 2.5 3.0 3.8 ns KQ 2.5 2.66 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 370 350 310 250 210 185 mA Curr (x32/x36) 430 410 365 290 240 200 mA t 4.0 4.2 4.5 5.5 6.5 7.5 ns KQ Flow 4.0 4.2 4.5 5.5 6.5 7.5 ns tCycle Through Curr (x18) 275 265 255 220 205 190 mA 2-1-1-1 Curr (x32/x36) 315 300 285 250 225 205 mA Rev: 1.03a 9/2013 1/24 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8160E18/32/36DGT-400/375/333/250/200/150 GS8160E18D 100-Pin TQFP Pinout 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 1M x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 67 FT SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.03a 9/2013 2/24 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see