GS8182T19BGD-400I GSI Technology

GS8182T19/37BD-435/400/375/333/300 435 MHz300 MHz 165-Bump BGA TM 18Mb SigmaDDR-II+ 1.8 V V Commercial Temp DD Industrial Temp Burst of 2 SRAM 1.8 V and 1.5 V I/O just one element in a family of low power, low voltage HSTL Features I/O SRAMs designed to operate at the speeds needed to 2.0 Clock Latency implement economical high performance networking systems. Simultaneous Read and Write SigmaDDR-II Interface Common I/O bus JEDEC-standard pinout and package Clocking and Addressing Schemes Double Data Rate interface Byte Write (x36 and x18) function The GS8182T19/37BD SigmaDDR-II+ SRAMs are Burst of 2 Read and Write synchronous devices. They employ two input register clock 1.8 V +100/100 mV core power supply inputs, K and K. K and K are independent single-ended clock 1.5 V or 1.8 V HSTL Interface inputs, not differential inputs to a single differential clock input Pipelined read operation with self-timed Late Write buffer. Fully coherent read and write pipelines ZQ pin for programmable output drive strength Each internal read and write operation in a SigmaDDR-II+ B2 IEEE 1149.1 JTAG-compliant Boundary Scan RAM is two times wider than the device I/O bus. An input data 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package bus de-multiplexer is used to accumulate incoming data before RoHS-compliant 165-bump BGA package available it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate SigmaDDR-II Family Overview output drivers as needed. Therefore the address field of a The GS8182T19/37BD are built in compliance with the SigmaDDR-II+ B2 RAM is always one address pin less than SigmaDDR-II+ SRAM pinout standard for Common I/O the advertised index depth (e.g., the 2M x 8 has a 1M synchronous SRAMs. They are 18,874,368-bit (18Mb) addressable index). SRAMs. The GS8182T19/37BD SigmaDDR-II SRAMs are Parameter Synopsis -435 -400 -375 -333 -300 tKHKH 2.3 ns 2.5 ns 2.67 ns 3.0 ns 3.3 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.03a 11/2011 1/27 2008, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8182T19/37BD-435/400/375/333/300 512K x 36 SigmaDDR-II+ SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA NC/SA A CQ R/W BW2 K BW1 LD SA CQ (144Mb) (36Mb) (72Mb) NC/SA B NC DQ27 DQ18 SA BW3 K BW0 SA NC DQ8 (288Mb) C NC NC DQ28 V SA NC SA V NC DQ17 DQ7 SS SS D NC DQ29 DQ19 V V V V V NC NC DQ16 SS SS SS SS SS E NC NC DQ20 V V V V V NC DQ15 DQ6 DDQ SS SS SS DDQ F NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ K NC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ L NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ M NC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS N NC DQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0 R TDO TCK SA SA SA NC SA SA SA TMS TDI 2 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8 BW1 controls writes to DQ9:DQ17 BW2 controls writes to DQ18:DQ26 BW3 controls writes to DQ27:DQ35 2. NC = Not connected Rev: 1.03a 11/2011 2/27 2008, GSI Technology Specifications cited are subject to change without notice. For latest documentation see