For new designs, please refer to the PALCE22V10 PALC22V10D Flash Erasable, Reprogrammable CMOS PAL Device erased and reprogrammed. The programmable macrocell pro- Features vides the capability of defining the architecture of each output Advanced second-generation PAL architecture individually. Each of the 10 potential outputs may be specified as registered or combinatorial. Polarity of each output may Low power also be individually selected, allowing complete flexibility of 90 mA max. commercial (10 ns) output configuration. Further configurability is provided 130 mA max. commercial (7.5 ns) through array configurable output enable for each potential output. This feature allows the 10 outputs to be reconfigured CMOS Flash EPROM technology for electrical erasabil- as inputs on an individual basis, or alternately used as a com- ity and reprogrammability bination I/O controlled by the programmable array. Variable product terms PALC22V10D features a variable product term architecture. 2 x(8 through 16) product terms There are 5 pairs of product term sums beginning at 8 product User-programmable macrocell terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PAL C Output polarity control 22V10D is optimized to the configurations found in a majority Individually selectable for registered or combinato- of applications without creating devices that burden the prod- uct term structures with unusable product terms and lower per- rial operation formance. Up to 22 input terms and 10 outputs Additional features of the Cypress PALC22V10D include a DIP, LCC, and PLCC available synchronous preset and an asynchronous reset product term. 7.5 ns commercial version These product terms are common to all macrocells, eliminat- ing the need to dedicate standard product terms for initializa- 5 ns t CO tion functions. The device automatically resets upon power-up. 5 ns t S The PALC22V10D, featuring programmable macrocells and 7.5 ns t PD variable product terms, provides a device with the flexibility to 133-MHz state machine implement logic functions in the 500- to 800-gate-array com- plexity. Since each of the 10 output pins may be individually 10 ns military and industrial versions configured as inputs on a temporary or permanent basis, func- 6 ns t CO tions requiring up to 21 inputs and only a single output and 6 ns t down to 12 inputs and 10 outputs are possible. The 10 poten- S tial outputs are enabled using product terms. Any output pin 10 ns t PD may be permanently selected as an output or arbitrarily en- 110-MHz state machine abled as an output and an input through the selective use of individual product terms associated with each output. Each of 15-ns commercial and military these outputs is achieved through an individual programmable versions macrocell. These macrocells are programmable to provide a 25-ns commercial and military combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed versions back into the array, providing current status information to the High reliability array. This information is available for establishing the next re- Proven Flash EPROM technology sult in applications such as control state machines. In a com- binatorial configuration, the combinatorial output or, if the out- 100% programming and functional testing put is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both program- Functional Description mable product term control of the outputs and variable product terms allows a significant gain in functional density through the The Cypress PALC22V10D is a CMOS Flash Erasable sec- use of programmable logic. ond-generation programmable array logic device. It is imple- Along with this increase in functional density, the Cypress mented with the familiar sum-of-products (AND-OR) logic PALC22V10D provides lower-power operation through the use structure and the programmable macrocell. of CMOS technology, and increased testability with Flash re- programmability. The PALC22V10D is executed in a 24-pin 300-mil molded DIP, PAL is a registered trademark of Advanced Micro Devices a 300-mil cerDIP, a 28-lead square ceramic leadless chip car- rier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The 22V10D can be electrically Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 July 1991 - Revised October 1995I I I I I I PALC22V10D Logic Block Diagram (PDIP/CDIP) V I III I I I III CP/I SS 12 11 10 98 7 6 5 432 1 PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 16 16 14 12 10 8 Reset Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Preset 13 14 15 16 17 18 19 20 21 22 23 24 I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V 9 8 7 6 5 4 3 2 1 0 CC V10D1 Pin Configuration PLCC LCC Top View Top View 4 3 2 1 2827 26 4 3 2 1 282726 I 5 25 I/O 2 I 5 25 I/O 2 I 6 24 I/O 3 I 6 24 I/O 3 I 7 23 I/O 4 I 7 23 I/O 4 8 NC 22 N/C 8 NC 22 N/C I 9 21 I/O 5 I 9 21 I/O 5 I 10 20 I/O 6 I 10 20 I/O 6 I 11 19 I/O 7 I 11 19 I/O 7 121314 1516 1718 12131415161718 V10D2 V10D3 Configuration Table Configuration Table Registered/Combinatorial Registered/Combinatorial C C Configuration 1 0 C C Configuration 1 0 1 0 Combinatorial/Active LOW 0 0 Registered/Active LOW 1 1 Combinatorial/Active HIGH 0 1 Registered/Active HIGH 2 I I V CP/I SS NC NC V CC I/O I/O 9 0 I/O8 I/O 1 I I V SS CP/I NC NC V CC I/O 9 I/O 0 I/O 8 I/O 1