PALCE16V8 Flash-Erasable Reprogrammable CMOS PAL Device Up to 16 input terms and eight outputs Features 7.5 ns coml version Active pull-up on data input pins 5 ns t CO Low power version (16V8L) 5 ns t S 7.5 ns t PD 55 mA max. commercial (10, 15, 25 ns) 125-MHz state machine 65 mA max. industrial (10, 15, 25 ns) 10 ns military/industrial versions 65 mA military (15 and 25 ns) 7 ns t CO 10 ns t Standard version has low power S 10 ns t PD 90 mA max. commercial (10, 15, 25 ns) 62-MHz state machine 115 mA max. commercial (7 ns) High reliability 130 mA max. military/industrial (10, 15, 25 ns) Proven Flash technology CMOS Flash technology for electrical erasability and 100% programming and functional testing reprogrammability PCI-compliant Functional Description User-programmable macrocell The Cypress PALCE16V8 is a CMOS Flash Electrical Output polarity control Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product Individually selectable for registered or combina- (AND-OR) logic structure and the programmable macrocell. torial operation Logic Block Diagram (PDIP/CDIP) GND I I I I I I I I CLK/I 8 7 6 5 4 3 2 1 0 10 98 7 6 5 432 1 PROGRAMMABLE AND ARRAY (64 x 32) 88 88 8 8 8 8 Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell 11 12 13 14 15 16 17 18 19 20 OE/I I/O I/O I/O I/O I/O I/O I/O I/O V 9 0 1 2 3 4 5 6 7 CC PLCC/LCC Pin Configurations DIP Top View Top View 1 20 CLK/I 0 V CC 2 19 I I/O 1 7 321 2019 3 18 I I/O 2 6 4 17 I 4 18 I/O I I/O 3 6 3 5 I 5 17 I/O 5 16 I/O 4 5 I 4 4 I 16 I/O 5 6 4 6 15 I/O I 3 5 I 7 I/O 6 15 3 14 7 I/O I 2 I 8 6 14 I/O 7 2 8 13 I I/O 7 1 9 10111213 9 12 I I/O 8 0 10 11 GND OE/I 9 Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600 Document : 38-03025 Rev. *A Revised April 22, 2004 I I 8 2 I GND 1 CLK/I OE/I 9 0 I/O V 0 CC I/O I/O 1 7 PALCE16V8 Selection Guide t ns t ns t ns I mA PD S CO CC Generic Part Number Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml Mil/Ind PALCE16V8-5 5 3 4 115 PALCE16V8-7 7.5 7 5 115 PALCE16V8-10 10 10 10 10 7 10 90 130 PALCE16V8-15 15 15 12 12 10 10 90 130 PALCE16V8-25 25 25 15 20 12 12 90 130 PALCE16V8L-15 15 15 12 12 10 12 55 65 PALCE16V8L-25 25 25 15 20 12 20 55 65 Shaded areas contain preliminary information. macrocell, the input/output pin associated with an adjacent Functional Description pin, or from the macrocell register itself. The PALCE16V8 is executed in a 20-pin 300-mil molded DIP, Power-Up Reset a 300-mil cerdip, a 20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip carrier. All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the The device provides up to 16 inputs and 8 outputs. The associated output pin will be HIGH due to active-LOW outputs. PALCE16V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function Electronic Signature as a superset to the familiar 20-pin PLDs such as 16L8, 16R8, 16R6, and 16R4. An electronic signature word is provided in the PALCE16V8 that consists of 64 bits of programmable memory that can The PALCE16V8 features 8 product terms per output and 32 contain user-defined data. input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable Security Bit control or as a data product term. A security bit is provided that defeats the readback of the There are a total of 18 architecture bits in the PALCE16V8 internal programmed pattern when the bit is programmed. macrocell two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture Low Power bits determine whether the macrocell functions as a register or The Cypress PALCE16V8 provides low-power operation combinatorial with inverting or noninverting output. The output through the use of CMOS technology, and increased testability enable control can come from an external pin or internally from with Flash reprogrammability. a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, Product Term Disable functioning as a dedicated input. Feedback paths are Product Term Disable (PTD) fuses are included for each selectable from either the input/output pin associated with the product term. The PTD fuses allow each product term to be individually disabled. Configuration Table CG CG CL0 Cell Configuration Devices Emulated 0 1 x 0 1 0 Registered Output Registered Med PALs 0 1 1 Combinatorial I/O Registered Med PALs 1 0 0 Combinatorial Output Small PALs 1 0 1 Input Small PALs 1 1 1 Combinatorial I/O 16L8 only Document : 38-03025 Rev. *A Page 2 of 13