Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY15B004Q 4-Kbit (512 8) Serial (SPI) Automotive F-RAM 4-Kbit (512 8) Serial (SPI) Automotive F-RAM Features Functional Description 4-Kbit ferroelectric random access memory (F-RAM) logically The CY15B004Q is a 4-Kbit nonvolatile memory employing an organized as 512 8 advanced ferroelectric process. A ferroelectric random access 13 High-endurance 10 trillion (10 ) read/writes memory or F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 121 years 121-year data retention (See Data Retention and Endurance on page 12) while eliminating the complexities, overhead, and system level reliability problems caused by serial flash, EEPROM, and other NoDelay writes nonvolatile memories. Advanced high-reliability ferroelectric process Very fast serial peripheral interface (SPI) Unlike serial flash and EEPROM, the CY15B004Q performs write operations at bus speed. No write delays are incurred. Data Up to 16 MHz frequency is written to the memory array immediately after each byte is Direct hardware replacement for serial flash and EEPROM successfully transferred to the device. The next bus cycle can Supports SPI mode 0 (0, 0) and mode 3 (1, 1) commence without the need for data polling. In addition, the Sophisticated write protection scheme product offers substantial write endurance compared with other Hardware protection using the Write Protect (WP) pin nonvolatile memories. The CY15B004Q is capable of supporting 13 Software protection using Write Disable instruction 10 read/write cycles, or 10 million times more write cycles than Software block protection for 1/4, 1/2, or entire array EEPROM. These capabilities make the CY15B004Q ideal for nonvolatile Low power consumption memory applications requiring frequent or rapid writes. 200 A active current at 1 MHz Examples range from data collection, where the number of write 6 A (typ) standby current at +85 C cycles may be critical, to demanding industrial controls where the Low-voltage operation: V = 3.0 V to 3.6 V DD long write time of serial flash or EEPROM can cause data loss. Automotive-E temperature: 40 C to +125 C The CY15B004Q provides substantial benefits to users of serial EEPROM or flash as a hardware drop-in replacement. The 8-pin small outline integrated circuit (SOIC) package CY15B004Q uses the high-speed SPI bus, which enhances the AEC Q100 Grade 1 compliant high-speed write capability of F-RAM technology. The device specifications are guaranteed over an automotive-e temperature Restriction of hazardous substances (RoHS) compliant range of 40 C to +125 C. Logic Block Diagram WP Instruction Decoder CS Clock Generator Control Logic HOLD Write Protect SCK 512 x 8 F-RAM Array Instruction Register 9 8 Address Register Counter SI SO Data OI/ Register 2 Nonvolatile Status Register Errata: The Write Enable Latch (WEL) bit in the Status Register of CY15B004Q part doesnt clear after executing the memory write (WRITE) operation at memory location(s) from 0x100 to 0x1FF. For more information, see Errata on page 19. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-10032 Rev. *D Revised November 20, 2018