Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY2304 3.3 V Zero Delay Buffer CY2304, 3.3 V Zero Delay Buffer required to be driven into the FBK pin, and can be obtained from Features one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be Zero input-output propagation delay, adjustable by capacitive less than 200 ps. load on FBK input The CY2304 has two banks of two outputs each. Multiple configurations The CY2304 PLL enters a power down state when there are no Multiple low-skew outputs rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 10 MHz to 133 MHz operating range 25 A of current draw. 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz Multiple CY2304 devices can accept the same input clock and Space-saving 8-pin 150-mil small outline integrated circuit distribute it in a system. In this case, the skew between the (SOIC) package outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations, as 3.3 V operation shown in Available Configurations. The CY2304-1 is the base Industrial temperature available part, where the output frequencies equal the reference if there is no counter in the feedback path. Functional Description The CY2304-2 allows the user to obtain Ref and 1/2x or 2x frequencies on each output bank. The exact configuration and The CY2304 is a 3.3 V zero delay buffer designed to distribute output frequencies depends on which output drives the feedback high-speed clocks in PC, workstation, datacom, telecom, and pin. other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an For a complete list of related documentation, click here. input clock presented on the REF pin. The PLL feedback is Logic Block Diagram FBK CLKA1 PLL REF CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Available Configurations Device FBK from Bank A Frequency Bank B Frequency CY2304-1 Bank A or B Reference Reference CY2304-2 Bank A Reference Reference/2 CY2304-2 Bank B 2 Reference Reference Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07247 Rev. *P Revised April 24, 2020