CY2305C CY2309C 3.3 V Zero Delay Clock Buffer 3.3 V Zero Delay Clock Buffer 100 MHz133 MHz frequencies and have higher drive than the Features -1 devices. All parts have on-chip phase locked loops (PLLs) 10 MHz to 100133 MHz operating range which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. Zero input and output propagation delay The CY2309C has two banks of four outputs each that are Multiple low skew outputs controlled by the select inputs as shown in the Select Input One input drives five outputs (CY2305C) Decoding on page 6. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the outputs One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C) by the select inputs for chip and system testing purposes. 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz) The CY2305C and CY2309C PLLs enter a power down mode Test mode to bypass phase locked loop (PLL) (CY2309C) only, when there are no rising edges on the REF input. In this state, see Select Input Decoding on page 6 the outputs are three-stated and the PLL is turned off. This results in less than 12.0 A of current draw for commercial Available in space saving 16-pin 150 Mil small outline temperature devices and 25.0 A for industrial and automotive-A integrated circuit (SOIC) or 4.4 mm thin shrunk small outline temperature parts. The CY2309C PLL shuts down in one package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C) additional case as shown in the Select Input Decoding on page 6. In the special case when S2:S1 is 1:0, the PLL is bypassed and 3.3 V operation REF is output from DC to the maximum allowable frequency. The Commercial, industrial and automotive-A flows available part behaves as a non-zero delay buffer in this mode and the outputs are not three-stated. Functional Description The CY2305C or CY2309C is available in two or three different The CY2305C and CY2309C are die replacement parts for configurations as shown in the Ordering Information on page 15. CY2305 and CY2309. The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H or CY2309-1H is the high drive version of the -1. Its rise and fall The CY2309C is a low-cost 3.3 V zero delay buffer designed to times are much faster than the -1. distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the For a complete list of related documentation, click here. CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to Logic Block Diagram CY2305C PLL CLKOUT REF CLK1 CLK2 CLK3 CLK4 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07672 Rev. *Q Revised April 27, 2017CY2305C CY2309C Logic Block Diagram CY2309C CLKOUT PLL MUX REF CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input CLKB2 Decoding CLKB3 S1 CLKB4 Document Number: 38-07672 Rev. *Q Page 2 of 22