CY2308 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer The CY2308 has two banks of four outputs each that is controlled Features by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is Zero input-output propagation delay, adjustable by capacitive three-stated. The input clock is directly applied to the output for load on FBK input chip and system testing purposes by the select inputs. Multiple configurations, see Available CY2308 Configurations The CY2308 PLL enters a power down state when there are no on page 4 for more details rising edges on the REF input. In this mode, all outputs are Multiple low skew outputs three-stated and the PLL is turned off resulting in less than 25 A of current draw. The PLL shuts down in two additional cases as Two banks of four outputs, three-stateable by two select inputs shown in the table Select Input Decoding on page 3. 10 MHz to 133 MHz operating range Multiple CY2308 devices accept the same input clock and distribute it in a system. In this case, the skew between the 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz) outputs of two devices is less than 700 ps. Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP The CY2308 is available in five different configurations as shown in the table Available CY2308 Configurations on page 4. 3.3 V operation The CY2308-1 is the base part where the output frequencies Industrial temperature available equal the reference if there is no counter in the feedback path. The CY2308-1H is the high drive version of the -1 and rise and Functional Description fall times on this device are much faster. The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute The CY2308-2 enables the user to obtain 2x and 1x frequencies high speed clocks in PC, workstation, datacom, telecom, and on each output bank. The exact configuration and output other high performance applications. frequencies depend on the users selection of output that drives The part has an on-chip PLL that locks to an input clock the feedback pin. presented on the REF pin. The PLL feedback is driven from The CY2308-3 enables the user to obtain 4x and 2x frequencies external FBK pin, so user has flexibility to choose any one of the on the outputs. outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250 ps and output-to-output The CY2308-4 enables the user to obtain 2x clocks on all skew is less than 200 ps. outputs. Thus, the part is extremely versatile and is used in a variety of applications. The CY2308-5H is a high drive version with REF/2 on both banks. For a complete list of related documentation, click here. Logic Block Diagram /2 FBK PLL REF MUX /2 CLKA1 CLKA2 Extra Divider (3, 4) CLKA3 Extra Divider (5H) CLKA4 S2 Select Input Decoding S1 /2 CLKB1 CLKB2 CLKB3 Extra Divider (2, 3) CLKB4 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07146 Rev. *T Revised December 7, 2017CY2308 Contents Pinouts ..............................................................................3 Ordering Information ...................................................... 13 Pin Definitions ..................................................................3 Ordering Code Definitions ......................................... 14 Select Input Decoding ......................................................3 Package Diagrams .......................................................... 15 Available CY2308 Configurations ...................................4 Acronyms ........................................................................16 Zero Delay and Skew Control ..........................................4 Document Conventions ................................................. 16 Maximum Ratings .............................................................5 Units of Measure ....................................................... 16 Operating Conditions .......................................................5 Errata ...............................................................................17 Electrical Characteristics .................................................5 Part Numbers Affected .............................................. 17 Operating Conditions .......................................................6 CY2308 Errata Summary .......................................... 17 Electrical Characteristics .................................................6 CY2308 Qualification Status ..................................... 17 Thermal Resistance ..........................................................6 Document History Page ................................................. 19 Switching Characteristics ................................................7 Sales, Solutions, and Legal Information ...................... 21 Switching Characteristics ................................................8 Worldwide Sales and Design Support ....................... 21 Switching Waveforms ......................................................9 Products ....................................................................21 Typical Duty Cycle and IDD Trends ..............................10 PSoCSolutions .......................................................21 Typical Duty Cycle and IDD Trends ..............................11 Cypress Developer Community ................................. 21 Test Circuits ....................................................................12 Technical Support ............................................................. 21 Document Number: 38-07146 Rev. *T Page 2 of 21