Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY2305 CY2309 Low Cost 3.3 V Zero Delay Buffer CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer Features Functional Description 10 MHz to 100/133 MHz operating range, compatible with CPU The CY2309 is a low-cost 3.3 V zero delay buffer designed to and PCI bus frequencies distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the Zero input-output propagation delay CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 60-ps typical cycle-to-cycle jitter (high drive) 100-/133 MHz frequencies, and have higher drive than the -1 Multiple low skew outputs devices. All parts have on-chip PLLs which lock to an input clock 85 ps typical output-to-output skew on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. One input drives five outputs (CY2305) One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) The CY2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in Select Input Decoding Compatible with Pentium-based systems on page 5. If all output clocks are not required, BankB can be Test Mode to bypass phase-locked loop (PLL) (CY2309) three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing Packages: purposes. 8-pin, 150-mil SOIC package (CY2305) The CY2305 and CY2309 PLLs enter a power-down mode when 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309) there are no rising edges on the REF input. In this state, the 3.3 V operation outputs are three-stated and the PLL is turned off, resulting in less than 25.0 A current draw for these parts. The CY2309 PLL Commercial and industrial temperature ranges shuts down in one additional case as shown in Select Input Decoding on page 5. Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2305/CY2309 is available in two or three different configurations, as shown in Ordering Information on page 16. The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. For a complete list of related documentation, click here. Logic Block Diagram CLKOUT PLL MUX REF CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input CLKB2 Decoding CLKB3 S1 CLKB4 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07140 Rev. *Y Revised June 12, 2020