CY23EP09 2.5 V or 3.3 V, 10 MHz220 MHz, Low Jitter, Nine-Output Zero Delay Buffer 2.5 V or 3.3 V, 10 MHz220 MHz, Low Jitter, Nine-Output Zero Delay Buffer Features Functional Description 10 MHz to 220 MHz maximum operating range The CY23EP09 is a 2.5 V or 3.3 V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or Zero input-output propagation delay, adjustable by loading on TSSOP package. The -1H version operates up to 220 (200) MHz CLKOUT pin frequencies at 3.3 V (2.5 V), and has higher drive than the -1 Multiple low-skew outputs devices. All parts have on-chip PLLs that lock to an input clock 45 ps typical output-output skew on the REF pin. The phase-locked loop (PLL) feedback is One input drives nine outputs, grouped as 4 + 4 + 1 on-chip and is obtained from the CLKOUT pad. 25 ps typical cycle-to-cycle jitter There are two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input 15 ps typical period jitter Decoding on page 4. If all output clocks are not required, BankB Standard and High drive strength options can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing Available in space-saving 16-pin 150-mil small outline purposes. integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages The PLL enters a power-down mode when there are no rising edges on the REF input (less than ~2 MHz). In this state, the 3.3 V or 2.5 V operation outputs are three-stated and the PLL is turned off, resulting in Industrial temperature available less than 25 A of current draw. In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves like a non-zero delay buffer in this mode, and the outputs are not tri-stated. The CY23EP09 is available in different configurations, as shown in the Ordering Information table. The CY23EP09-1 is the base part. The CY23EP09-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5 V input-tolerant applications For a complete list of related documentation, click here. Block Diagram CLKOUT PLL MUX REF CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input CLKB2 Decoding CLKB3 S1 CLKB4 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07760 Rev. *G Revised December 14, 2017CY23EP09 Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 15 Pin Definitions ..................................................................3 Ordering Code Definitions ......................................... 15 Select Input Decoding ......................................................4 Package Diagrams .......................................................... 16 Zero Delay and Skew Control ..........................................4 Acronyms ........................................................................17 Absolute Maximum Conditions .......................................5 Document Conventions ................................................. 17 Operating Conditions .......................................................5 Units of Measure ....................................................... 17 Electrical Specifications ..................................................6 Document History Page ................................................. 18 Electrical Specifications ..................................................6 Sales, Solutions, and Legal Information ...................... 19 Thermal Resistance ..........................................................7 Worldwide Sales and Design Support ....................... 19 Test Circuits ......................................................................7 Products ....................................................................19 Electrical Specifications ..................................................8 PSoCSolutions .......................................................19 Switching Waveforms ....................................................10 Cypress Developer Community ................................. 19 Supplemental Parametric Information ..........................11 Technical Support ..................................................... 19 Document Number: 38-07760 Rev. *G Page 2 of 19