CY23FP12 200 MHz Field Programmable Zero Delay Buffer 200 MHz Field Programmable Zero Delay Buffer Features Functional Description Fully field-programmable The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock Input and output dividers distribution. The integrated PLL is designed for low jitter and Inverting/non-inverting outputs optimized for noise rejection. These parameters are critical for Phase-locked loop (PLL) or fanout buffer configuration reference clock distribution in systems using high performance 10 MHz to 200 MHz operating range ASICs and microprocessors. The CY23FP12 is fully programmable through volume or Split 2.5 V or 3.3 V outputs prototype programmers, enabling the user to define an Two LVCMOS reference inputs application-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output Twelve low skew outputs inversions, and output drive strengths. For additional flexibility, 35 ps typical output-to-output skew (same frequency) the user can mix and match multiple functions listed in Table 2, 110 ps typical cycle-cycle jitter (same frequency) and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature enables Three-stateable outputs the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12 also Less than 50 A shutdown current features a proprietary auto power down circuit that shuts down Spread aware the device in case of a REF failure, resulting in less than 50 A of current draw. 28-pin SSOP The CY23FP12 provides 12 outputs grouped in two banks with 3.3 V operation separate power supply pins which can be connected independently to either a 2.5 V or a 3.3 V rail. Industrial temperature available Selectable reference input is a fault tolerance feature which enables glitch-free switch over to a secondary clock source when REFSEL is asserted/de-asserted. For a complete list of related documentation, click here. Logic Block Diagram VDDA VDDC CLKA0 Lock Detect CLKA1 CLKA2 CLKA3 REFSEL CLKA4 CLKA5 REF1 M 100 to 1 400MHz REF2 VSSA PLL FBK N 2 VDDB 3 4 CLKB0 X CLKB1 CLKB2 CLKB3 Test Logic CLKB4 Function Selection S 2:1 CLKB5 VSSC VSSB Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07246 Rev. *K Revised March 17, 2017 CY23FP12 Contents Pin Configuration .............................................................3 Ordering Information ...................................................... 15 Pin Description .................................................................4 Ordering Code Definitions ......................................... 15 Basic PLL Block Diagram ................................................5 Package Drawing and Dimensions ............................... 16 Programmable Functions ................................................6 Acronyms ........................................................................17 Field Programming the CY23FP12 .............................8 Document Conventions ................................................. 17 CyberClocks Software ..............................................8 Units of Measure ....................................................... 17 CY3672-USB Development Kit ...................................8 Document History Page ................................................. 18 CY23FP12 Frequency Calculation ..................................8 Sales, Solutions, and Legal Information ...................... 19 Absolute Maximum Conditions .......................................9 Worldwide Sales and Design Support ....................... 19 Operating Conditions .......................................................9 Products ....................................................................19 DC Electrical Specifications ..........................................10 PSoC Solutions ...................................................... 19 Thermal Resistance ........................................................10 Cypress Developer Community ................................. 19 Switching Characteristics ..............................................11 Technical Support ..................................................... 19 Switching Waveforms ....................................................13 Test Circuits ....................................................................14 Document Number: 38-07246 Rev. *K Page 2 of 19