CY23FS04 Failsafe 2.5 V/3.3 V Zero Delay Buffer Failsafe 2.5 V/3.3 V Zero Delay Buffer Features Functional Description Internal digital controlled crystal oscillator (DCXO) for The CY23FS04 is a FailSafe zero delay buffer with two continuous glitch-free operation reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where Zero input-output propagation delay continuous operation is required in the event of a primary clock failure. Low jitter (35 ps max RMS) outputs The continuous, glitch-free operation is achieved by using a Low output-to-output skew (200 ps max) DCXO. This serves as a redundant clock source in the event of 4.17 MHz to 166.7 MHz reference input a reference clock failure by maintaining the last frequency and phase information of the reference clock. Supports industry standard input crystals The unique feature of the CY23FS04 is that the DCXO is the 166.7 MHz outputs primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is 5 V tolerant Inputs restored, the DCXO automatically resynchronizes to the external Phase-locked loop (PLL) bypass mode clock. The frequency of the crystal that is connected to the DCXO must Dual reference inputs be an integer factor of the frequency of the reference clock. This 16-Pin thin shrunk small outline package (TSSOP) factor is set by two select lines: S 2:1 , see Configuration Table on page 3. The output power supply V can be connected to DD 2.5 V or 3.3 V output power supplies either 2.5 V or 3.3 V. VDDC is the power supply pin for internal 3.3 V core power supply circuits and must be connected to 3.3 V. For a complete list of related documentation, click here. Industrial temperature range Logic Block Diagram XIN XOUT REFSEL DCXO 2 REF1 CLKA 2:1 REF2 TM Failsafe PLL Block 2 CLKB 2:1 FBK FAIL /SAFE Decoder 2 S 2:1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07304 Rev. *M Revised December 14, 2017CY23FS04 Contents Pin Configuration .............................................................3 Package Diagram ............................................................ 13 Pin Definitions ..................................................................3 Acronyms ........................................................................14 Configuration Table ..........................................................3 Document Conventions ................................................. 14 FailSafe Function ..............................................................4 Units of Measure ....................................................... 14 XTAL Selection Criteria and Application Example ........6 Document History Page ................................................. 15 Absolute Maximum Conditions .......................................8 Sales, Solutions, and Legal Information ...................... 16 Recommended Pullable Crystal Specifications ............8 Worldwide Sales and Design Support ....................... 16 Operating Conditions .......................................................9 Products ....................................................................16 Electrical Characteristics .................................................9 PSoCSolutions .......................................................16 Thermal Resistance ..........................................................9 Cypress Developer Community ................................. 16 Switching Characteristics ..............................................10 Technical Support ..................................................... 16 Switching Waveforms ....................................................11 Ordering Information ......................................................12 Ordering Code Definitions .........................................12 Document Number: 38-07304 Rev. *M Page 2 of 16