CY23FS08 Failsafe 2.5 V/3.3 V Zero Delay Buffer Failsafe 2.5 V/3.3 V Zero Delay Buffer Features Functional Description Internal DCXO for continuous glitch-free operation The CY23FS08 is a FailSafe Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The Zero input-output propagation delay device provides an optimum solution for applications where continuous operation is required in the event of a primary clock 100 ps typical output cycle-to-cycle jitter failure. 110 ps typical output-output skew Continuous, glitch-free operation is achieved by using a DCXO, 1 MHz to 200 MHz reference input which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and Supports industry standard input crystals phase information of the reference clock. 200 MHz (commercial), 166 MHz (industrial) outputs The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized 5 V tolerant inputs (phase-aligned) to the external reference clock. When this Phase-locked loop (PLL) bypass mode external clock is restored, the DCXO automatically resynchronizes to the external clock. Dual reference inputs The frequency of the crystal connected to the DCXO, must be 28-pin SSOP chosen to be an integer factor of the frequency of the reference clock. This factor is set by four select lines: S 4:1 . see Split 2.5 V or 3.3 V output power supplies Configuration Table on page 4. The CY23FS08 has three split 3.3 V core power supply power supplies one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except Industrial temperature available VDDC can be connected to either 2.5 V or 3.3 V. VDDC is the power supply pin for internal circuits and must be connected to 3.3 V. For a complete list of related documentation, click here. Logic Block Diagram XIN XOUT REFSEL DCXO REF1 4 CLKA 1:4 TM Failsafe REF2 PLL Block 4 CLKB 1:4 FBK Decoder FAIL /SAFE 4 S 4:1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07518 Rev. *J Revised May 27, 2016 CY23FS08 Contents Pinouts ..............................................................................3 Package Diagram ............................................................ 14 Pin Definitions ..................................................................3 Acronyms ........................................................................15 Configuration Table ..........................................................4 Document Conventions ................................................. 15 FailSafe Function ..............................................................4 Units of Measure ....................................................... 15 XTAL Selection Criteria and Application Example ........7 Document History Page ................................................. 16 Absolute Maximum Conditions .......................................9 Sales, Solutions, and Legal Information ...................... 17 Recommended Pullable Crystal Specifications ............9 Worldwide Sales and Design Support ....................... 17 Operating Conditions .....................................................10 Products ....................................................................17 DC Electrical Characteristics ........................................10 PSoCSolutions .......................................................17 Thermal Resistance ........................................................10 Cypress Developer Community ................................. 17 Switching Characteristics ..............................................11 Technical Support ..................................................... 17 Switching Waveforms ....................................................12 Ordering Information ......................................................13 Ordering Code Definitions .........................................13 Document Number: 38-07518 Rev. *J Page 2 of 17