Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY24488 Quad-PLL Clock Generator with Two-Wire Serial Interface Quad-PLL Clock Generator with Two-Wire Serial Interface Features Functional Description Three output frequencies plus reference out The CY24488 generates up to three independent clock frequencies, and a buffered copy of the reference crystal Programmable output frequencies through two-wire serial frequency, from a single crystal or reference input. Five clock interface output pins are available, which allows some frequencies to be driven on two or more output pins. Outputs can also be Output frequencies from 4.9152 to 148.5 MHz individually enabled or disabled. When a CLK output is Uses an external 27 MHz crystal or 27 MHz input clock individually disabled, it drives low. Optional analog VCXO The analog voltage controlled crystal oscillator (VCXO) allows you to pull the reference crystal to a frequency that is slightly Programmable output drive strength to minimize EMI higher or lower than nominal. This causes all output clocks to shift by an equivalent parts-per-million (PPM). The VCXO is The equivalent without a serial port is the CY22388/89/91 controlled by the analog control voltage applied to the V pin. IN 16-pin TSSOP package For applications that do not require the VCXO functionality, it can be disabled. 3.3 V operation with 2.5 V output buffer option A serial programming interface (SPI) permits in-system Benefits configuration of the device by writing to internal registers. It is used to set the output frequencies, enable and disable outputs, Meets most Digital Set Top Box, DVD Recorder, and DTV enable and disable the VCXO feature, and more. The SPI application requirements provides volatile programming. When powered down, the device reverts to its preSPI state. When the system is powered back up, Multiple high performance PLLs allow synthesis of unrelated the SPI registers need to be configured again. Specific frequencies configuration details are given in the following sections of this data sheet. Integration eliminates the need for external loop filter components Customers may contact their Cypress FAE or salesperson for any frequency that is not listed in this data sheet. The data sheet Complete VCXO solution with 120 ppm (typical pull range) can be updated with a new hex code for the requested frequency. For a complete list of related documentation, click here. Applications and Frequencies Output Clock Application Frequencies (MHz) CLKC Audio 6.144, 8.192, 11.2896, 12.288, 16.384, 16.9344, 18.432, 22.5792, 24.576, 33.8688, 36.864 iLink 24.576 HDMI 25.175, 28.322 CLKD Video 27, 27.027, 54, 54.054, 81 USB 12, 24, 48 Video-Pixel Frequency 74.25/1.001, 74.25, 148.5/1.001, 148.5 Modem 4.9152, 11.0592 iLink 24.576 CLKE Video 13.5, 27, 54, 81, 108 Ethernet 25 PCI 33.3333, 66.6666 Processor 20, 30, 40, 50, 60, 80, 100 CLKF See CLKC/D/E REFOUT or Copy of CLKC, CLKD or CLKE CLKG See CLKC/D/E REFOUT or Copy of CLKC, CLKD or CLKE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-09608 Rev. *H Revised December 14, 2017