Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Programmable Spread Spectrum Clock Generator for EMI Reduction Features Functional Description Wide Operating Output (SSCLK) Frequency Range The CY25200 is a programmable clock generator with spread spectrum capability. Spread spectrum modulates the output 3 to 200 MHz clock frequency over a small range, spreading the energy and Programmable Spread Spectrum with nominal 31.5-kHz reducing the energy peak. This is a powerful technique to reduce modulation frequency EMI in a variety of applications. Center Spread: 0.25% to 2.5% It uses either an external reference clock or a crystal for an input. It also uses a PLL to generate a spread spectrum output clock Down Spread: 0.5% to 5.0% that can be a different frequency than the input. Up to six output clocks are available and up to two of them can be REFCLKs Input frequency range (copies of the input clock, without spread). External crystal: 8 to 30 MHz fundamental crystals External reference: 8 to 166 MHz clock The CY25200 is highly configurable. Programmable variables include the input and output frequencies, spread percentage, Integrated phase-locked loop (PLL) center spread or down spread, and control pin functions. The oscillator pin capacitance can also be programmed to match the Programmable crystal load capacitor tuning array load capacitance requirement (C ) of the crystal, eliminating the L Low cycle-to-cycle jitter need for external capacitors. 3.3-V operation with 2.5-V Output Clock Drive Option Available features include Output Enable, Power Down, Spread On/Off, Frequency Select, and the option to power some output Spread Spectrum On and Off function clocks at 2.5 V. Power Down or Output Enable function Programmability enables fast prototyping, which is particularly useful when doing EMC testing and determining the optimal Output Frequency Select option spread settings. Field-Programmable For a complete list of related documentation, click here. Package: 16-pin TSSOP Logic Block Diagram 7 SSCLK1 Divider Bank 1 8 SSCLK2 Output 9 SSCLK3 Select XIN/CLKIN 1 Q Matrix OSC. 12 SSCLK4 VCO XOUT 16 P C XOUT C Divider XIN Bank 2 PLL 14 SSCLK5/REFOUT/CP2 15 SSCLK6/REFOUT/CP3 2 35 11 6 410 13 AVSS VSS VDD AVDD VDDL VSSL CP0 CP1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07633 Rev. *M Revised January 21, 2019
