CY25561 Spread Spectrum Clock Generator Spread Spectrum Clock Generator This reduction in radiated energy can significantly reduce the Features cost of complying with regulatory requirements and time to market without degrading the system performance. 50 to 166 MHz operating frequency range CY25561 is a very simple and versatile device to use. The Wide range of spread selections: 9 frequency and spread percentage range is selected by Accepts clock and crystal inputs programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic Low power dissipation levels to select one of the nine available spread percentage 70 mW - Typ at 66 MHz ranges. Refer to Frequency and Spread Percentage Selection (Center Spread) on page 3 for programming details. Frequency spread disable function CY25561 is intended for use with applications with a reference Center spread modulation frequency in the range of 50 to 166 MHz. Low cycle-to-cycle jitter A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 8-pin SOIC Package and S1 digital control inputs. Functional Description The output spread (frequency modulation) is symmetrically centered on the input frequency. CY25561 is a spread spectrum clock generator (SSCG) IC used Spread spectrum clock control (SSCC) function enables or to reduce electromagnetic Interference (EMI) found in todays disables the frequency spread and is provided for easy high speed digital electronic systems. comparison of system performance during EMI testing. CY25561 uses a Cypress proprietary phase-locked loop (PLL) CY25561 is available in an eight-pin SOIC package with a 0 C and spread spectrum clock (SSC) technology to synthesize and to 70 C operating temperature range. frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and For a complete list of related documentation, click here. harmonic frequencies of clock (SSCLK) is reduced. Logic Block Diagram 300 K REFERENCE Xin/ 1 DIVIDER CLK Loop PD CP Filter Xout 8 MODULATION FEEDBACK vco CONTROL DIVIDER VDD 2 INPUT DIVIDER DECODER & 4 SSCLK LOGIC MUX VSS 3 VDD VDD 20K 20K 20K 20K VSS VSS 5 6 7 SSCC S1 S0 Note: Refer to the CY25560 data sheet for operation at frequencies from 25 to100 MHz. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07242 Rev. *K Revised February 8, 2018 CY25561 Contents Pin Configuration .............................................................3 Ordering Information ........................................................ 9 Pin Definitions ..................................................................3 Ordering Code Definitions ........................................... 9 Frequency and Spread Percentage Selection Package Drawing and Dimensions ............................... 10 (Center Spread) .................................................................3 Acronyms ........................................................................ 11 Tri-level Logic ...................................................................4 Document Conventions ................................................. 11 SSCG Theory of Operation ..............................................4 Units of Measure ....................................................... 11 EMI ..............................................................................4 Document History Page ................................................. 12 SSCG ..........................................................................4 Sales, Solutions, and Legal Information ...................... 13 Modulation Rate ..........................................................5 Worldwide Sales and Design Support ....................... 13 CY25561 Application Schematic .....................................6 Products .................................................................... 13 Absolute Maximum Ratings ............................................7 PSoC Solutions ...................................................... 13 DC Electrical Characteristics ..........................................7 Cypress Developer Community ................................. 13 Thermal Resistance ..........................................................7 Technical Support ..................................................... 13 XIN/CLK DC Specifications ..............................................8 Electrical Timing Characteristics ....................................8 Document Number: 38-07242 Rev. *K Page 2 of 13