QB0 VDDQA VDDQB QA0 NC VSS VSS QA1 QC3 VDDQA VDDQC QA2 QC2 FB SEL1 VSS VSS QC1 QA3 VDDQC VDDQA QC0 QA4 VSS AVSS VCO SEL FB SEL0 774 CY29774 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer The CY29774 features two reference clock inputs and pro- Features vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Output frequency range: 8.3 MHz to 125 MHz Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Input frequency range: 4.2 MHz to 62.5 MHz Table. These dividers allow output to input ratios of 6:1, 4:1, 2.5V or 3.3V operation 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out- Split 2.5V/3.3V outputs put can drive 50 series or parallel terminated transmission 14 Clock outputs: Drive up to 28 clock lines lines. For series terminated transmission lines, each output 1 Feedback clock output can drive one or two traces giving the device an effective fanout of 1:28. 2 LVCMOS reference clock inputs 150 ps max output-output skew The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range PLL bypass mode of output frequencies from 8.3 MHz to 125 MHz. For normal Spread Aware operation, the external feedback input, FB IN, is connected to Output enable/disable the feedback output, FB OUT. The internal VCO is running at Pin compatible with MPC9774 multiples of the input reference clock set by the feedback di- Industrial temperature range: 40C to +85C vider, see Frequency Table. 52-Pin 1.0-mm TQFP package When PLL EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static Description and the minimum input clock frequency specification does not apply. The CY29774 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. Pin Configuration Block Diagram VCO SEL PLL EN TCLK SEL TCLK0 TCLK1 PLL 2 52 51 50 49 48 47 46 45 44 43 42 41 40 CLK 2 / 4 QA0 200 - STOP 4 VSS VSS 1 39 QA1 500MHz QB1 FB IN MR /OE 2 38 QA2 CLK STP VDDQB 3 37 QA3 QB2 SELB 4 36 QA4 SELA SELC VSS 5 35 QB3 CLK PLL EN 6 34 2 / 4 STOP QB0 VDDQB SELA 7 33 CY29774 QB1 TCLK SEL 8 32 QB4 SELB QB2 9 31 FB IN TCLK0 QB3 TCLK1 10 30 VSS QB4 11 29 FB OUT NC VDD 12 28 VDDFB CLK 4 / 6 QC0 STOP 13 27 NC AVDD QC1 14 15 16 17 18 19 20 21 22 23 24 25 26 SELC QC2 QC3 CLK STP FB OUT 4 / 6 / 8 / 12 FB SEL(1,0) MR /OE Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 Document : 38-07479 Rev. ** Revised April 28, 2003 + Feedback CY29774 1 Pin Description Pin Name I/O Type Description 9 TCLK0 I, PD LVCMOS LVCMOS/LVTTL reference clock input 10 TCLK1 I, PU LVCMOS LVCMOS/LVTTL reference clock input 16, 18, 21, QA(4:0) O LVCMOS Clock output bank A 23, 25 32, 34, 36, QB(4:0) O LVCMOS Clock output bank B 38, 40 44, 46, 48, QC(3:0) O LVCMOS Clock output bank C 50 29 FB OUT O LVCMOS Feedback clock output. Connect to FB IN for normal operation. 31 FB IN I, PU LVCMOS Feedback clock input. Connect to FB OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 2 MR /OE I, PU LVCMOS Output enable/disable input. See Table 2. 3CLK STP I, PU LVCMOS Clock stop enable/disable input. See Table 2. 6 PLL EN I, PU LVCMOS PLL enable/disable input. See Table 2. 8 TCLK SEL I, PD LVCMOS Reference select input. See Table 2. 52 VCO SEL I, PD LVCMOS VCO divider select input. See Table 2. 7, 4, 5 SEL(A:C) I, PD LVCMOS Frequency select input, Bank (A:C). See Table 3. 20, 14 FB SEL(1,0) I, PD LVCMOS Feedback dividers select input. See Table 4. 2,3 17, 22, 26 VDDQA Supply VDD 2.5V or 3.3V Power supply for bank A output clocks 2,3 33, 37, 41 VDDQB Supply VDD 2.5V or 3.3V Power supply for bank B output clocks 2,3 45, 49 VDDQC Supply VDD 2.5V or 3.3V Power supply for bank C output clocks 2,3 28 VDDFB Supply VDD 2.5V or 3.3V Power supply for feedback output clock 2,3 13 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL 2,3 12 VDD Supply VDD 2.5V or 3.3V Power supply for core and inputs 15 AVSS Supply Ground Analog Ground 1, 19, 24, VSS Supply Ground Common Ground 30, 35, 39, 43, 47, 51 11, 27, 42 NC No Connection Notes: 1. PU = Internal pull up, PD = Internal pull down 2. A 0.1- F bypass capacitor should be placed as close as possible to each positive power pin (<0.2). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply pins. Document : 38-07479 Rev. ** Page 2 of 9 + Feedback