CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description All output pair skew <100 ps typical (250 ps maximum) The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. 3.75 MHz to 80 MHz output operation These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high User selectable output functions performance computer systems. Each of the eight individual Selectable skew to 18 ns drivers, arranged in four pairs of user controllable outputs, can Inverted and non-inverted drive terminated transmission lines with impedances as low as Operation at 12 and 14 input frequency 50. They can deliver minimal and specified output skews and Operation at 2 and 4 input frequency (input as low as full swing logic levels (CY7B991 TTL or CY7B992 CMOS). 3.75 MHz) Each output is hardwired to one of the nine delay or function Zero input to output delay configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs that skew up to 6 time 50% duty cycle outputs units from their nominal zero skew position. The completely Outputs drive 50 terminated lines integrated PLL allows cancellation of external load and transmission line delay effects. When this zero delay capability Low operating current of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to 12 32-pin PLCC package time units. Jitter < 200 ps peak-to-peak (< 25 ps RMS) Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that are multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. For a complete list of related documentation, click here. Logic Block Diagram TEST PHASE FB VCO AND FREQ FILTER TIME UNIT DET REF GENERATOR FS 4Q0 4F0 4F1 SELECT 4Q1 INPUTS (THREE SKEW LEVEL) 3Q0 3F0 3F1 3Q1 SELECT 2Q0 2F0 MATRIX 2F1 2Q1 1Q0 1F0 1F1 1Q1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07138 Rev. *O Revised April 18, 2018CY7B991 CY7B992 Contents Pinouts ..............................................................................3 AC Timing Diagrams ...................................................... 12 Pin Definitions ..................................................................3 Operational Mode Descriptions .................................... 13 Block Diagram Description ..............................................4 Ordering Information ...................................................... 17 Phase Frequency Detector and Filter ..........................4 Ordering Code Definitions ......................................... 17 VCO and Time Unit Generator ....................................4 Package Diagram ............................................................ 18 Skew Select Matrix ......................................................4 Acronyms ........................................................................ 19 Test Mode ..........................................................................5 Document Conventions ................................................. 19 Maximum Ratings .............................................................6 Units of Measure ....................................................... 19 Operating Range ...............................................................6 Document History Page ................................................. 20 Electrical Characteristics .................................................6 Sales, Solutions, and Legal Information ...................... 22 Capacitance ......................................................................8 Worldwide Sales and Design Support ....................... 22 Thermal Resistance ..........................................................8 Products .................................................................... 22 AC Test Loads and Waveforms .......................................8 PSoC Solutions ...................................................... 22 Switching Characteristics ................................................9 Cypress Developer Community ................................. 22 Switching Characteristics ..............................................10 Technical Support ..................................................... 22 Switching Characteristics ..............................................11 Document Number: 38-07138 Rev. *O Page 2 of 22