CY7B9945V RoboClock High-Speed Multi-Phase PLL Clock Buffer High-Speed Multi-Phase PLL Clock Buffer Features Functional Description 500 ps max Total Timing Budget (TTB) window The CY7B9945V high-speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple 24 MHz200 MHz input and Output Operation output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer Low Output-output skew <200 ps and communication systems. 10 + 1 LVTTL outputs driving 50 terminated lines The device features a guaranteed maximum TTB window Dedicated feedback output specifying all occurrences of output clocks. This includes the input reference clock across variations in output frequency, Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns supply voltage, operating temperature, input edge rate, and process. 3.3-V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable Reference Inputs Ten configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal Multiply or Divide Ratios of 1 through 6, 8, 10, and 12 and specified output skews at LVTTL levels. The outputs are Individual Output Bank Disable arranged in two banks of four and six outputs. These banks enable a divide function of 1 to 12, with phase adjustments in Output High Impedance Option for Testing Purposes 625ps1300 ps increments up to 10.4 ns. The dedicated feedback output enables divide-by functionality from 1 to 12 and Integrated Phase Locked Loop (PLL) with Lock Indicator limited phase adjustments. However, if needed, any one of the Low Cycle-cycle jitter (<100 ps peak-peak) ten outputs can be connected to the feedback input as well as driving other inputs. 3.3 V Operation Selectable reference input is a fault tolerant feature that enables Industrial Temperature Range: 40 C to +85 C smooth change over to a secondary clock source when the primary clock source is not in operation. The reference inputs 52-pin 1.4 mm TQFP package and feedback inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout. For a complete list of related documentation, click here. Logic Block Diagram FS 3 REFA+ REFA- LO C K REFB+ PLL REFB- REFSEL FBK MODE Divide FBF0 3 and QF Phase FBD S0 3 Select FBD S1 3 1Q 0 3 1F0 1F1 3 1Q 1 Divide 1D S0 3 and Phase 1D S1 3 Select 1Q 2 1F2 3 1Q 3 1F3 3 DIS1 2Q 0 2Q 1 3 2F0 Divide 2F1 3 2Q 2 and Phase 2D S 0 3 2Q 3 Select 2D S1 3 2Q 4 2Q 5 DIS2 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07336 Rev. *O Revised June 19, 2017 CY7B9945V RoboClock Contents Pinouts ..............................................................................3 AC Timing Diagram ........................................................ 13 Pin Definitions ..................................................................4 Ordering Information ...................................................... 14 Block Diagram Description ..............................................5 Ordering Code Definitions ......................................... 14 Time Unit Definition .....................................................5 Package Diagram ............................................................ 15 Divide and Phase Select Matrix ..................................6 Acronyms ........................................................................16 Output Disable Description ..........................................8 Document Conventions ................................................. 16 Lock Detect Output Description ...................................8 Units of Measure ....................................................... 16 Factory Test Mode Description ...................................8 Document History Page ................................................. 17 Safe Operating Zone ...................................................8 Sales, Solutions, and Legal Information ...................... 18 Absolute Maximum Conditions .......................................9 Worldwide Sales and Design Support ....................... 18 Operating Range ...............................................................9 Products ....................................................................18 Electrical Characteristics .................................................9 PSoC Solutions ...................................................... 18 Capacitance ....................................................................10 Cypress Developer Community ................................. 18 Thermal Resistance ........................................................10 Technical Support ..................................................... 18 AC Test Loads and Waveforms .....................................10 Switching Characteristics ..............................................11 Document Number: 38-07336 Rev. *O Page 2 of 18