CY7B993V/CY7B994V RoboClock High-Speed Multi-Phase PLL Clock Buffer High-Speed Multi-Phase PLL Clock Buffer Features Functional Description 500 ps Max Total Timing Budget (TTB) window The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user selectable control over system clock 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz functions. This multiple output clock driver provides the system (CY7B994V) Input/Output Operation integrator with functions necessary to optimize the timing of high-performance computer and communication systems. Matched Pair Output Skew < 200 ps These devices feature a guaranteed maximum TTB window Zero Input-to-Output Delay specifying all occurrences of output clocks with respect to the 18 LVTTL Outputs Driving 50 Terminated Lines input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and 16 Outputs at 200 MHz: Commercial Temperature process. 6 Outputs at 200 MHz: Industrial Temperature Eighteen configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering 3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable minimal and specified output skews at LVTTL levels. The outputs are Reference Inputs arranged in five banks. Banks 1 to 4 of four outputs allow a divide Phase Adjustments in 625 ps/1300 ps Steps Up to 10.4 ns function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One Multiply/Divide Ratios of 16, 8, 10, 12 of the output banks also includes an independent clock invert function. The feedback bank consists of two outputs, which Individual Output Bank Disable allows divide-by functionality from 1 to 12 and limited phase Output High Impedance Option for Testing Purposes adjustments. Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs. Fully Integrated Phase Locked Loop (PLL) with Lock Indicator Selectable reference input is a fault tolerance feature that allows <50-ps Typical Cycle-to-Cycle Jitter smooth change-over to secondary clock source, when the primary clock source is not in operation. The reference inputs Single 3.3V 10% Supply and feedback inputs are configurable to accommodate both 100-pin TQFP Package LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout. 100-pin BGA Package For a complete list of related documentation, click here. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07127 Rev. *O Revised November 27, 2017CY7B993V/CY7B994V RoboClock Logic Block Diagram FBKA+ FBKA LOCK FBKB+ FBKB Control Logic Phase FBSEL VCO Divide and Phase Filter Freq. Generator REFA+ Detector REFA REFB+ FS 3 REFB OUTPUT MODE 3 REFSEL Divide and FBF0 3 QFA0 Phase FBDS0 3 Feedback Bank QFA1 Select 3 FBDS1 Matrix FBDIS 4QA0 4F0 3 Divide and 4QA1 4F1 3 Phase Bank 4 3 4DS0 4QB0 Select 4DS1 3 4QB1 Matrix DIS4 3QA0 3F0 3 Divide and 3QA1 3F1 3 Phase Bank 3 3DS0 3 Select 3QB0 3DS1 3 Matrix 3QB1 DIS3 INV3 3 2QA0 3 2F0 Divide and 2QA1 3 2F1 Phase Bank 2 3 2DS0 Select 2QB0 3 2DS1 Matrix 2QB1 DIS2 1QA0 1F0 3 Divide and 1QA1 1F1 3 Phase 3 Bank 1 1DS0 Select 1QB0 3 1DS1 Matrix 1QB1 DIS1 Document Number: 38-07127 Rev. *O Page 2 of 23