CY7B995 RoboClock 2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer 2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer Features Functional Description 2.5 V or 3.3 V operation The CY7B995 RoboClock is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase Split output bank power supplies programmability which is necessary to optimize the timing of high performance computer and communication systems. Output frequency range: 6 MHz to 200 MHz The user can program both the frequency and the phase of the 45 ps typical cycle-cycle jitter output banks through nF 0:1 and DS 0:1 pins. The adjustable 2% max output duty cycle phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to Selectable output drive strength feedback to achieve different reference frequency multiplication, and divide ratios and zero input-output delay. Selectable positive or negative edge synchronization The device also features split output bank power supplies, which Eight LVTTL outputs driving 50 terminated lines enable the user to run two banks (1Qn and 2Qn) at a power LVCMOS/LVTTL over-voltage tolerant reference input supply level, different from that of the other two banks (3Qn and 4Qn). The three-level PE/HD pin also controls the Selectable phase-locked loop (PLL) frequency range and lock synchronization of the output signals to either the rising, or the indicator falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) Phase adjustments in 625/1250 ps steps up to 7.5 ns increases the output current from 12 mA to 24 mA. (1-6, 8, 10, 12) x multiply and (1/2,1/4) x divide ratios For a complete list of related documentation, click here. Spread-Spectrum compatible Power down mode Selectable reference divider Industrial temperature range: 40 C to +85 C 44-pin TQFP package Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07337 Rev. *I Revised May 3, 2016 CY7B995 RoboClock Logic Block Diagram TEST PE/HD FS VDDQ1 3 PD /DIV 3 3 3 /R REF LOCK PLL /N FB 3 3 DS1:0 1Q0 3 Phase 1F1:0 3 Select 1Q1 2Q0 3 Phase 2F1:0 3 Select 2Q1 3Q0 3 Phase 3F1:0 Select 3 3Q1 and /K VDDQ3 4Q0 3 Phase 4F1:0 Select 3 and /M 4Q1 sOE VDDQ4 Document Number: 38-07337 Rev. *I Page 2 of 19