CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Space saving 32-pin 7 mm 7 mm TQFP Featuresb 32-pin PLCC High-speed, low-power, first-in, first-out (FIFO) Available in Pb-Free Packages memories 64 x 9 (CY7C4421V) Functional Description 256 x 9 (CY7C4201V) The CY7C42X1V are high-speed, low-power, FIFO memories 512 x 9 (CY7C4211V) with clocked read and write interfaces. All are nine bits wide. 1K x 9 (CY7C4221V) Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data 2K x 9 (CY7C4231V) buffering needs, including high-speed data acquisition, multi- 4K x 9 (CY7C4241V) processor interfaces, and communications buffering. 8K x 9 (CY7C4251V) These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port High-speed 66-MHz operation (15-ns read/write cycle is controlled by a Free-Running Clock (WCLK) and two Write time) Enable pins (WEN1, WEN2/LD). Low power (I = 20 mA) CC When WEN1 is LOW and WEN2/LD is HIGH, data is written 3.3V operation for low power consumption and easy into the FIFO on the rising edge of the WCLK signal. While integration into low-voltage systems WEN1, WEN2/LD is held active, data is continually written into 5V-tolerant inputs V = 5V the FIFO on each WCLK cycle. The output port is controlled in IH max a similar manner by a Free-Running Read Clock (RCLK) and Fully asynchronous and simultaneous read and write two Read Enable Pins (REN1, REN2). In addition, the operation CY7C42X1V has an Output Enable Pin (OE). The Read Empty, Full, and Programmable Almost Empty and (RCLK) and Write (WCLK) clocks may be tied together for Almost Full status flags single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock TTL compatible frequencies up to 66 MHz are achievable. Output Enable (OE) pin Depth expansion is possible using one enable input for system Independent read and write enable pins control, while the other enable is controlled by expansion logic Center power and ground pins for reduced noise to direct the flow of data. Width expansion capability Pin Configuration Logic Block Diagram D 0 8 PLCC Top View INPUT REGISTER 4 321 323130 D 1 29 RS 5 D 28 0 6 WEN1 PAF 7 27 WCLK WCLK WEN1 WEN2/LD PAE 8 26 WEN2/LD GND 9 V 25 CC FLAG REN1 10 24 Q 8 PROGRAM RCLK 11 23 Q REGISTER 7 REN2 12 22 Q 6 WRITE OE 21 Q 13 5 CONTROL 14151617181920 EF PAE FLAG LOGIC PAF Dual Port FF RAM Array 64 x 9 WRITE READ 8Kx 9 POINTER POINTER RESET RS LOGIC THREE-STATE READ OUTPUTREGISTER CONTROL OE Q 0 8 RCLK REN1 REN2 Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600 Document : 38-06010 Rev. *B Revised July 14, 2005 + Feedback D2 EF FF D3 Q 0 D 4 Q 1 D5 Q 2 D6 D Q 7 3 Q D 4 8CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Selection Guide CY7C42X1V-15 CY7C42X1V-25 CY7C42X1V-35 Unit Maximum Frequency 66.7 40 28.6 MHz Maximum Access Time 11 15 20 ns Minimum Cycle Time 15 25 35 ns Minimum Data or Enable Set-up 4 6 7 ns Minimum Data or Enable Hold 1 1 2 ns Maximum Flag Delay 10 15 20 ns Active Power Supply Current Commercial 20 20 20 mA CY7C4421V CY7C4201V CY7C4211V CY7C4221V CY7C4231V CY7C4241V CY7C4251V Density 64 x 9 256 x 9 512 x 9 1K x 9 2K x 9 4K x 9 8K x 9 Pin Definitions Signal Name Description I/O Description D Data Inputs I Data Inputs for 9-bit bus. 08 Q Data Outputs O Data Outputs for 9-bit bus. 08 WEN1 Write Enable 1 I The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. WEN2/LD Write Enable 2 I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this Dual Mode Pin pin operates as a control to write or read the programmable flag offsets. WEN1 must be Load I LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. REN1, REN2 Read Enable I Enables the device for Read operation. Inputs WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag offset register. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value Almost Empty programmed into the FIFO. PAF Programmable O When PAF is LOW, the FIFO is almost full based on the almost full offset value Almost Full programmed into the FIFO. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable I When OE is LOW, the FIFOs data outputs drive the bus to which they are connected. If OE is HIGH, the FIFOs outputs are in High Z (high-impedance) state. When entering or exiting the Empty and Almost Empty states, Functional Description (continued) the flags are updated exclusively by the RCLK. The flags The CY7C42X1V provides four status pins: Empty, Full, Almost denoting Almost Full and Full states are updated exclusively Empty, Almost Full. The Almost Empty/Almost Full flags are by WCLK. The synchronous flag architecture guarantees that programmable to single word granularity. The programmable flags the flags maintain their status for at least one cycle default to Empty-7 and Full-7. All configurations are fabricated using an advanced 0.65 The flags are synchronous, i.e., they change state relative to P-Well CMOS technology. Input ESD protection is greater than either the Read Clock (RCLK) or the Write Clock (WCLK). 2001V, and latch-up is prevented by the use of guard rings. Document : 38-06010 Rev. *B Page 2 of 18 + Feedback