CY7C63722C CY7C63723C CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller Features enCoRe USB - enhanced Component Reduction SPI serial communication block Internal oscillator eliminates the need for an external crystal Master or slave operation or resonator 2 Mbit/s transfers Interface can auto-configure to operate as PS/2 or USB with- Four 8-bit Input Capture registers out the need for external components to switch between modes (no General Purpose I/O GPIO pins needed to man- Two registers each for two input pins age dual mode capability) Capture timer setting with five prescaler settings Internal 3.3 V regulator for USB pull-up resistor Separate registers for rising and falling edge capture Configurable GPIO for real-world interface without external Simplifies interface to RF inputs for wireless applications components Internal low-power wake-up timer during suspend mode Flexible, cost-effective solution for applications that combine Periodic wake-up with no external components PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others. Optional 6-MHz internal oscillator mode Allows fast start-up from suspend mode USB Specification Compliance Watchdog Reset (WDR) Conforms to USB Specification, Version 2.0 Conforms to USB HID Specification, Version 1.1 Low-voltage Reset at 3.75 V Supports one low-speed USB device address and three data endpoints Internal brown-out reset for suspend mode Integrated USB transceiver Improved output drivers to reduce EMI 3.3 V regulated output for USB pull-up resistor Operating voltage from 4.0V to 5.5VDC 8-bit RISC microcontroller Operating temperature from 0C to 70C Harvard architecture 6-MHz external ceramic resonator or internal clock mode CY7C63723C available in 18-pin SOIC, 18-pin PDIP 12-MHz internal CPU clock CY7C63743C available in 24-pin SOIC, 24-pin PDIP, 24-pin Internal memory QSOP 256 bytes of RAM 8 Kbytes of EPROM CY7C63722C available in DIE form Interface can auto-configure to operate as PS/2 or USB Industry standard programmer support No external components for switching between PS/2 and USB modes No GPIO pins needed to manage dual mode capability I/O ports Up to 16 versatile GPIO pins, individually configurable High current drive on any GPIO pin: 50 mA/pin current sink Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs Maskable interrupts on all I/O pins Errata: For information on silicon errata, see Errata on page 53. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-08022 Rev. *K Revised April 21, 2017 CY7C63722C CY7C63723C CY7C63743C Logic Block Diagram XTALIN/P2.1 XTALOUT Wake-Up Internal Xtal RAM 12-bit Capture SPI Oscillator Timer 256 Byte Oscillator Timer Timers 8-bit EPROM RISC 8K Byte Core Brown-out Reset Interrupt USB Port 1 Port 0 Controller GPIO GPIO Engine Watch Dog Timer USB & 3.3V Low PS/2 Regulator Voltage Xcvr Reset P1.0P1.7 P0.0P0.7 D+,D VREG/P2.0 Document Number: 38-08022 Rev. *K Page 2 of 56