CY7C67300
EZ-Host Programmable Embedded
USB Host and Peripheral Controller with
Automotive AEC Grade Support
SPI support in both master and slave
EZ-Host Features
On-chip 16-bit DMA/mailbox data path interface
Single chip programmable USB dual-role (Host/Peripheral)
controller with two configurable Serial Interface Engines (SIEs)
Supports 12 MHz external crystal or clock
and four USB ports
3.3V operation
Support for USB On-The-Go (OTG) protocol
Automotive AEC grade option (40C to 85C)
On-chip 48 MHz 16-bit processor with dynamically switchable
Package option100-pin TQFP
clock speed
Configurable IO block supporting a variety of IO options or up
Typical Applications
to 32 bits of General Purpose IO (GPIO)
EZ-Host is a very powerful and flexible dual role USB controller
4K x 16 internal masked ROM containing built in BIOS that
that supports a wide variety of applications. It is primarily
2
supports a communication ready state with access to I C
intended to enable host capability in applications such as:
EEPROM Interface, external ROM, UART, or USB
Set top boxes
8K x 16 internal RAM for code and data buffering
Printers
Extended memory interface port for external SRAM and ROM
KVM switches
16-bit parallel Host Port Interface (HPI) with a DMA/mailbox
data path for an external processor to directly access all of the Kiosks
on-chip memory and control on-chip SIEs
Automotive applications
Fast serial port supports from 9600 baud to 2.0M baud
Wireless access points
Block Diagram
CY7C67300
Timer 0 Timer 1
nRESET
Control
UART I/F
I2C
EEPROM I/F
Watchdog
CY16
HSS I/F
16-bit RISC CORE
Vbus, ID
OTG
PWM
D+,D- USB-A
GPIO [31:0]
SIE1
SPI I/F
D+,D- USB-B
Host/
Peripheral
IDE I/F
USB Ports
D+,D- USB-A
4Kx16 8Kx16
ROM BIOS RAM
HPI I/F
SIE2
USB-B
D+,D-
GPIO
External MEM I/F
Mobile
X1 (SRAM/ROM)
PLL
Power
X2
Booster
SHARED INPUT/OUTPUT PINS
A[15:0] D[15:0] CTRL[9:0]
Errata: For information on silicon errata, see Errata on page 107. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-08015 Rev. *P Revised January 18, 2018
SHARED INPUT/OUTPUT PINSCY7C67300
Contents
Introduction .......................................................................3 HSS Registers ........................................................... 62
Functional Overview ........................................................3 HPI Registers ............................................................ 68
Processor Core ...........................................................3 SPI Registers ............................................................ 72
Clocking .......................................................................3 UART Registers ........................................................ 80
Memory .......................................................................3 PWM Registers ......................................................... 82
Interrupts .....................................................................3 Pin Diagram .................................................................... 86
General Timers and Watchdog Timer .........................3 Pin Descriptions ............................................................. 86
Power Management ....................................................3 Absolute Maximum Ratings .......................................... 90
Interface Descriptions ......................................................3 Operating Conditions ..................................................... 90
USB Interface ..............................................................5 Crystal Requirements (XTALIN, XTALOUT) ................. 90
OTG Interface ..............................................................6 DC Characteristics ........................................................ 90
External Memory Interface ..........................................6 USB Transceiver ....................................................... 91
General Purpose IO Interface (GPIO) .........................9 AC Timing Characteristics ............................................. 92
UART Interface [3] .......................................................9 Reset Timing ........................................................... 92
I2C EEPROM Interface [4] ..........................................9 Clock Timing ............................................................. 92
[24]
Serial Peripheral Interface ...........................................9 SRAM Read Cycle .............................................. 93
[26]
High-Speed Serial Interface ......................................10 SRAM Write Cycle .............................................. 94
Programmable Pulse/PWM Interface ........................10 I2C EEPROM Timing-Serial IO ................................. 95
Host Port Interface ....................................................11 HPI (Host Port Interface) Write Cycle Timing ........... 96
IDE Interface .............................................................11 HPI (Host Port Interface) Read Cycle Timing ........... 97
Charge Pump Interface .............................................12 IDE Timing ................................................................. 98
Booster Interface .......................................................13 HSS BYTE Mode Transmit ........................................98
Crystal Interface ........................................................13 HSS Block Mode Transmit ........................................98
Boot Configuration Interface ......................................14 HSS BYTE and BLOCK Mode Receive .................... 98
Operational Modes ....................................................14 Hardware CTS/RTS Handshake ............................... 99
Power Savings and Reset Description .........................15 Register Summary .......................................................... 99
Power Saving Mode Description ...............................15 Ordering Information .................................................... 104
Sleep .........................................................................15 Ordering Code Definitions ....................................... 104
External (Remote) Wakeup Source ...........................16 Package Diagram .......................................................... 105
Power-On-Reset Description .....................................16 Acronyms ...................................................................... 106
Reset Pin ...................................................................16 Document Conventions ............................................... 106
USB Reset .................................................................16 Units of Measure ..................................................... 106
Memory Map ....................................................................16 Errata ............................................................................. 107
Mapping .....................................................................16 Part Numbers Affected ............................................ 107
Registers .........................................................................18 CY7C67300 Qualification Status ............................. 107
Processor Control Registers .....................................18 CY7C67300 Errata Summary .................................. 107
External Memory Registers .......................................25 Document History Page ............................................... 117
Timer Registers .........................................................27 Sales, Solutions, and Legal Information .................... 119
General USB Registers [10] ......................................29 Worldwide Sales and Design Support ..................... 119
USB Host Only Registers [11] ...................................32 Products .................................................................. 119
USB Device Only Registers ......................................43 PSoC Solutions .................................................... 119
OTG Control Registers [13] .......................................54 Cypress Developer Community ............................... 119
GPIO Registers .........................................................56 Technical Support ................................................... 119
IDE Registers ............................................................59
Document Number: 38-08015 Rev. *P Page 2 of 119