CY7C9689A TAXI-compatible HOTLink Transceiver Features Second-generation HOTLink technology synchronous Transmit FIFO. Data is read from the Transmit FIFO and is encoded using embedded 4B/5B or 5B/6B AMD AM7968/7969 TAXIchip-compatible encoders to improve its serial transmission characteristics. These encoded characters are then serialized, converted to 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport NRZI, and output from two PECL-compatible differential 10-bit or 12-bit NRZI pre-encoded (bypass) data transport transmission line drivers at a bit-rate of either 10 or 20 times the input reference clock in 8-bit (or 10-bit bypass) mode, or Synchronous TTL parallel interface 12 or 24 times the reference clock in 10-bit (or 12-bit bypass) Embedded/bypassable 256-character Transmit and Receive mode. FIFOs The receive section of the CY7C9689A HOTLink accepts a serial bit-stream from one of two PECL compatible differential 50- to 200-MBaud serial signaling rate line receivers and, using a completely integrated PLL clock Internal phase-locked loops (PLLs) with no external PLL synchronizer, recovers the timing information necessary for components data reconstruction. The recovered bit stream is converted from NRZI to NRZ, deserialized, framed into characters, Dual differential PECL-compatible serial inputs and outputs 4B/5B or 5B/6B decoded, and checked for transmission Compatible with fiber-optic modules and copper cables errors. The recovered 8- or 10-bit decoded characters are then written to an internal Receive FIFO, and presented to the Built-in self-test (BIST) for link testing destination host system. Link Quality Indicator The integrated 4B/5B and 5B/6B encoder/decoder may be bypassed (disabled) for systems that present externally Single +5.0 V 10%supply encoded or scrambled data at the parallel interface. With the 100-pin TQFP encoder bypassed, the pre-encoded parallel data stream is converted to and from a serial NRZI stream. The embedded Pb-free package option available FIFOs may also be bypassed (disabled) to create a reference-locked serial transmission link. For those systems Functional Description requiring even greater FIFO storage capability, external FIFOs may be directly coupled to the CY7C9689A through the The CY7C9689A HOTLink Transceiver is a point-to-point parallel interface without the need for additional glue-logic. communications building block allowing the transfer of data The TTL parallel I/O interface may be configured as either a over high-speed serial links (optical fiber, balanced, and FIFO (configurable for depth expansion through external unbalanced copper transmission lines) at speeds ranging FIFOs) or as a pipeline register extender. The FIFO between 50 and 200 MBaud. The transmit section accepts configurations are optimized for transport of time-independent parallel data of selectable widths and converts it to serial data, (asynchronous) 8- or 10-bit character-oriented data across a while the receiver section accepts serial data and converts it link. A Built-In Self-Test (BIST) pattern generator and checker to parallel data of selectable widths. Figure 1 illustrates typical allows for testing of the high-speed serial data paths in both connections between two independent host systems and the transmit and receive sections, and across the corresponding CY7C9689A parts. The CY7C9689A provides interconnecting links. enhanced technology, increased functionality, a higher level of integration, higher data rates, and lower power dissipation HOTLink devices are ideal for a variety of applications where over the AMD AM7968/7969 TAXIchip products. parallel interfaces can be replaced with high-speed, point-to-point serial links. Some applications include The transmit section of the CY7C9689A HOTLink can be interconnecting workstations, backplanes, servers, mass configured to accept either 8- or 10-bit data characters on each storage, and video transmission equipment. clock cycle, and stores the parallel data into an internal Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-02020 Rev. *G Revised June 27, 2014 CY7C9689A Contents TAXI HOTLink Transceiver Logic Block Diagram .......3 CY7C9689A Transmitter Switching Pin Configuration .............................................................4 Characteristics Over the Operating Range .................... 28 Pin Descriptions ...............................................................5 CY7C9689A HOTLink Transmitter CY7C9689A HOTLink Operation ...................................14 Switching Waveforms .................................................... 28 Overview ...................................................................14 CY7C9689A HOTLink Receiver Transmit Data Path ...................................................14 Switching Waveforms .................................................... 33 Receive Data Interface ..............................................14 Output Enable Timi.............................................. ng 34 Oscillator Speed Selection ........................................14 Functional Description ................................................... 36 CY7C9689A TAXI HOTLink Transceiver CY7C9689A TAXI HOTLink Transmit-Path Operating Mode Block Diagram Description ............................................14 Descriptions .................................................................... 37 Transmit FIFO ...........................................................16 Synchronous Encoded .............................................. 37 Encoder Block ...........................................................16 Synchronous Pre-encoded ........................................ 37 Transmit Shifter .........................................................17 Asynchronous Encoded ............................................ 37 Routing Matrix ...........................................................17 CY7C9689A TAXI HOTLink Receive-Path Operating Mode Serial Line Drivers .....................................................17 Descriptions .................................................................... 37 Transmit PLL Clock Multiplier ....................................18 Synchronous Decoded .............................................. 37 Transmit Control State Machine ................................18 Synchronous Undecoded .......................................... 38 Serial Line Receivers ................................................18 Asynchronous Decoded ............................................ 38 Signal Detect .............................................................18 Asynchronous Undecoded ........................................ 38 Clock/Data Recovery .................................................19 BIST Operation and Reporting ...................................... 38 Clock Divider .............................................................19 BIST Enable Inputs ................................................... 39 Deserializer/Framer ...................................................19 BIST Transmit Path ................................................... 39 Decoder Block ...........................................................19 BIST Receive Path .................................................... 40 Receive Control State Machine .................................20 BIST Three-state Control .......................................... 40 Receive FIFO ............................................................20 Bus Interfacing ............................................................... 40 Receive Input Register ..............................................20 Shared Bus Interface Concept .................................. 41 Receive Output Register ...........................................20 Device Selection ........................................................ 41 Maximum Ratings ...........................................................23 Address Match and FIFO Flag Access...................... 41 Operating Range .......................................................23 Device Selection ........................................................ 42 CY7C9689A DC Electrical Characteristics Transmit Data Selection ............................................ 42 Over the Operating Range .............................................23 Receive Data Selection ............................................. 43 AC Test Loads and Waveforms .....................................24 FIFO Reset Address Match ....................................... 45 Capacitance 16 ..............................................................24 FIFO Reset Sequence ............................................... 46 CY7C9689A Transmitter TTL Switching Characteristics, Transmit FIFO Reset Sequence ................................ 46 FIFO Enabled Over the Operating Range .......................25 Receive FIFO Reset Sequence ................................. 49 CY7C9689A Receiver TTL Switching Characteristics, FIFO Printed Circuit Board Layout Suggestions ................. 50 Enabled Over the Operating Range ................................25 Ordering Information ...................................................... 51 CY7C9689A Transmitter TTL Switching Characteristics, Ordering Code Definitions ......................................... 51 FIFO Bypassed Over the Operating Range .................... 26 Package Diagram ............................................................ 51 CY7C9689A Receiver TTL Switching Characteristics, FIFO Acronyms ....................................................................... 52 Bypassed Over the Operating Range .............................26 Units of Measure ....................................................... 52 CY7C9689A REFCLK Input Switching Sales, Solutions, and Legal Information ...................... 54 Characteristics Over the Operating Range ....................27 Worldwide Sales and Design Support ....................... 54 CY7C9689A Receiver Switching Characteristics Over the Products ....................................................................54 Operating Range ..............................................................27 PSoC Solutions ......................................................... 54 Document : 38-02020 Rev. *G Page 2 of 54