CY8CLED04G01-56LTXI Infineon

CY8CLED04D01/CY8CLED04D02/CY8CLED04G01 CY8CLED03D01/CY8CLED03D02/CY8CLED03G01 CY8CLED02D01/CY8CLED01D01 PowerPSoC Intelligent LED Driver PowerPSoC Intelligent LED Driver 1. Features Integrated power peripherals Up to 9-bit DACs Applications Four internal 32 V low side N-Channel power Programmable gain amplifiers Stage LED lighting FETs Programmable filters and comparators Architectural LED lighting R 0.5 for 1.0 A devices 8 to 32-bit timers and counters General purpose LED lighting DS(ON) Up to 2 MHz configurable switching frequency Complex peripherals by combining blocks Automotive and emergency vehicle LED lighting Four hysteretic controllers Configurable to all GPIO pins Landscape LED lighting Independently programmable upper and Display LED lighting Programmable pin configurations lower thresholds Effects LED lighting 25 mA sink, 10 mA source on all GPIO and func- Programmable minimum ON/OFF timers Signage LED lighting tion pins Four low side gate drivers with programmable Pull-up, pull-down, high Z, strong, or open drain Device options drive strength drive modes on all GPIO and function pins CY8CLED04D0x Four precision high side current sense amplifiers Up to 10 analog inputs on GPIO Four internal FETs with 0.5 A and 1.0 A Three 16-bit LED dimming modulators: PrISM, Two 30 mA analog outputs on GPIO options DMM, and PWM Configurable interrupt on all GPIO Four external gate drivers Six fast response (100 ns) voltage comparators CY8CLED04G01 Flexible on-chip memory Six 8-bit reference DACs Four external gate drivers 16 K flash program storage 50,000 erase / write Built-in switching regulator eliminates external CY8CLED03D0x cycles 5 V supply Three internal FETs with 0.5 A and 1.0 A 1 K SRAM data storage Multiple topologies including floating load buck, options In-system serial programming (ISSP) floating load buck-boost, and boost Three external gate drivers Partial flash updates M8C CPU core CY8CLED03G01 Flexible protection modes Processor speeds up to 24 MHz Three external gate drivers EEPROM emulation in flash CY8CLED02D01 Advanced peripherals (PSoC Blocks) Complete development tools Two 1.0 A internal FETs Capacitive sensing application capability Free development software (PSoC Designer) Two external gate drivers DMX512 interface Full-featured, in-circuit emulator (ICE) and 2 CY8CLED01D01 I C master or slave programmer One 1.0 A internal FET Full-duplex UARTs Full-speed emulation One external gate driver Multiple SPI masters or slaves Complex breakpoint structure Integrated temperature sensor 128 KB trace memory 56-pin QFN package Up to 12-bit ADCs 6 to 12-bit incremental ADCs Figure 1-1. PowerPSoC Architectural Block Diagram Analog Port 2 Port 1 Port 0 FN0 Drivers CSA CSA SYSTEM BUS Analog Mux Bus PWM Controller Gate Power Global Digital Interconnect Logic Core Channels (LV) Driver(L V) FETs (HV) Global Analog Interconnect PrISM/ DMM/ PSoC CORE Clock Signals PWM SRAM Flash Nonvolatile Hysteretic Supervisory ROM DAC Decoder GDRV PWM (1 K bytes) (SROM) Memory(1 6 K) CPU Analog Block (M8C) Interrupt Sleep and Core Watchdog C1 Controller System Bus C2 Hysteretic DAC C3 GDRV 24 MHz Internal Main Internal Low Speed PWM Oscillator(I MO) Oscillator ( ILO) C4 Multiple Clock Sources C5 C6 ANALOG SYSTEM DIGITAL SYSTEM Hysteretic Comparator GDRV DAC PWM Analog PSoC Bank Analog Digital PSoC Block Array Block Array Ref DBB00 DBB 01 DCB 02 DCB 03 DAC CT CT SC SC DBB01 DBB 11 DCB 12 DCB13 AINX DAC Hysteretic 2 Digital Rows SC SC DAC PWM GDRV DAC 2Analog Columns DAC Bank Vref POR and LVD Internal Digital MACs Decimator IO Analog POWER PERIPHERALS I2C Voltage SW Regulator Clocks (2) (Type2) Multiplexer System Resets Reference PSoC SYSTEM RESOURCES CSA CSA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-46319 Rev. *R Revised April 16, 2015 Interupt Bus Power System Analog Bus Power System Digital Bus Chbond busCY8CLED04D01/CY8CLED04D02/CY8CLED04G01 CY8CLED03D01/CY8CLED03D02/CY8CLED03G01 CY8CLED02D01/CY8CLED01D01 2. Contents Logic Block Diagrams.................................................... 3 Register Map Bank 0 Table .................................... 28 Register Map Bank 1 Table: User Space................ 29 PowerPSoC Functional Overview ................................. 9 Electrical Specifications .............................................. 30 Power Peripherals .......................................................... 9 Absolute Maximum Ratings..................................... 30 Hysteretic Controllers................................................ 9 Operating Temperature........................................... 31 Low Side N-Channel FETs...................................... 10 External Gate Drivers .............................................. 10 Electrical Characteristics............................................. 31 Dimming Modulation Schemes................................ 10 System Level........................................................... 31 Current Sense Amplifier .......................................... 10 Chip Level ............................................................... 31 Voltage Comparators .............................................. 11 Power Peripheral Low Side N-Channel FET........... 33 Reference DACs ..................................................... 11 Power Peripheral External Power FET Driver......... 34 Built-in Switching Regulator .................................... 11 Power Peripheral Hysteretic Controller ................... 34 Analog Multiplexer................................................... 11 Power Peripheral Comparator................................. 35 Digital Multiplexer .................................................... 12 Power Peripheral Current Sense Amplifier.............. 37 Function Pins (FN0 0:3 ) ......................................... 12 Power Peripheral PWM/PrISM/DMM Specification Table ....................................................................... 38 PSoC Core..................................................................... 13 Power Peripheral Reference DAC Specification ..... 39 Digital System ......................................................... 13 Power Peripheral Built-in Switching Regulator........ 39 Analog System ........................................................ 13 General Purpose I/O / Function Pin I/O................... 42 Analog Multiplexer System...................................... 14 PSoC Core Operational Amplifier Specifications .... 43 Additional System Resources ................................. 14 PSoC Core Low Power Comparator ....................... 44 Applications .................................................................. 15 PSoC Core Analog Output Buffer............................ 45 PowerPSoC Device Characteristics............................ 17 PSoC Core Analog Reference ................................ 47 PSoC Core Analog Block ........................................ 47 Getting Started.............................................................. 18 PSoC Core POR and LVD ...................................... 48 Application Notes .................................................... 18 PSoC Core Programming Specifications ................ 48 Development Kits .................................................... 18 PSoC Core Digital Block Specifications .................. 49 Training ................................................................... 18 PSoC Core I2C Specifications ................................ 50 CYPros Consultants................................................ 18 Technical Support ................................................... 18 Ordering Information.................................................... 51 Ordering Code Definitions....................................... 51 Development Tools ...................................................... 18 PSoC Designer Software Subsystems.................... 18 Packaging Information................................................. 52 In-Circuit Emulator................................................... 19 Packaging Dimensions............................................ 52 Thermal Impedance ................................................ 52 Designing with User Modules ..................................... 19 Solder Reflow Peak Temperature ........................... 52 Pin Information ............................................................. 20 Acronyms...................................................................... 53 CY8CLED04D0x 56-Pin Part Pinout (without OCD) 20 CY8CLED04G01 56-Pin Part Pinout (without OCD) 21 Document Conventions ............................................... 53 CY8CLED04DOCD1 56-Pin Part Pinout (with OCD) 22 Units of Measure ..................................................... 53 CY8CLED03D0x 56-Pin Part Pinout (without OCD) 23 Document History Page............................................... 55 CY8CLED03G01 56-Pin Part Pinout (without OCD) 24 Sales, Solutions, and Legal Information .................... 56 CY8CLED02D01 56-Pin Part Pinout (without OCD) 25 Worldwide Sales and Design Support..................... 56 CY8CLED01D01 56-Pin Part Pinout (without OCD) 26 Products .................................................................. 56 Register General Conventions .................................... 27 PSoC Solutions .................................................... 56 Abbreviations Used ................................................. 27 Cypress Developer Community............................... 56 Register Naming Conventions................................. 27 Technical Support ................................................... 56 Register Mapping Tables ........................................ 27 Document Number: 001-46319 Rev. *R Page 2 of 55